Consider the following instruction sequence: Add R3, R4, R5 (R4+R5->R3) Or R2, R4, R5 (R4 OR R5->R2) Add R1, R2, R3 (R2+R3->R1)
Assuming no data forwarding, what are all the data dependencies?
Isn't the only data dependency from the third instruction where R2 and R3 have not been written back yet. So to correct this dependency a stall of 3 cycles would be needed before the third instruction could decode the registers. If data forwarding was allowed, the register values could be forwarded and no stalls would occur, correct? Am I missing something? Is there a data dependency between the first two instructions since R4 and R5 are used in both?
For the following instructions: Load R2, 20(R5) Add R4, R3, R2 Store R4, 20(R5)
Would the data dependencies be that for instruction 2, you would need to stall 3 cycles before R2 would be available, and for instruction 3 you would need to stall 6 cycles before R4 was available? If data forwarding was permitted there would be one stall in instruction 2 for the memory from the first instruction to be forwarded to the execute portion of the 2nd instruction. This would then lead to one stall for the third instruction during the decode phase. Is this also correct?