# Classic RISC pipeline question

Consider the following instruction sequence:
Or R2, R4, R5 (R4 OR R5->R2)


Assuming no data forwarding, what are all the data dependencies?

Isn't the only data dependency from the third instruction where R2 and R3 have not been written back yet. So to correct this dependency a stall of 3 cycles would be needed before the third instruction could decode the registers. If data forwarding was allowed, the register values could be forwarded and no stalls would occur, correct? Am I missing something? Is there a data dependency between the first two instructions since R4 and R5 are used in both?

For the following instructions:
Store R4, 20(R5)


Would the data dependencies be that for instruction 2, you would need to stall 3 cycles before R2 would be available, and for instruction 3 you would need to stall 6 cycles before R4 was available? If data forwarding was permitted there would be one stall in instruction 2 for the memory from the first instruction to be forwarded to the execute portion of the 2nd instruction. This would then lead to one stall for the third instruction during the decode phase. Is this also correct?

Thanks

In the first part of the question, you are correct that the only data dependencies are from the first instruction to the third instruction and from the second instruction to the third instruction. You are also correct that there is no data dependency between the first and second instructions.

Similarly in the second part you are correct that there is a data dependence from the first instruction to the second and from the second to the third.

Data forwarding has nothing to do with which instructions have data dependencies. There is always a data dependency from an instruction that produces a value to any other instructions that consume that value.

Given that there are data dependencies the presence (or lack of) forwarding impacts performance. But I can't tell you how much stalling you would need because I don't know your pipeline latencies. Forwarding typically reduces the amount of stalling required.

In the Wikipedia's Classic RISC Pipeline page, two solutions to the dependency problem are described: bypassing and pipeline interlock.

Bypassing can forward the output of the second instruction and make it available to the third, without a penalty. Naturally the more distant dependency to the first instruction is covered.

Pipeline interlock will require a one cycle stall for the second to third dependency, since it bypasses from the later MEM stage, but there should be no stall for the first to third dependency which is an extra cycle ahead already.