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  1. How to estimate the via pad diameter? I am using pi*d = trace width I have decided but Saturn PCB Design calculator is giving very lower current value at that diameter.
  2. How to decide the via hole diameter?
  3. If I am using parallel vias for high currents, will the current divide equally?
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  • \$\begingroup\$ Default via barrel plating thickness probably won't be the same as copper track thickness (weight, e.g. 1oz/sqft), and it will not scale linearly with decreasing via diameter, although it might be good enough in some cases. So pi*d might not work for you. Also different fabricators will have different capabilities regarding plating. Best to get their advice in advance of a design. \$\endgroup\$
    – anon33
    Feb 1 at 11:50
  • \$\begingroup\$ For 3, what frequency are we talking about? \$\endgroup\$
    – winny
    Feb 1 at 12:11

2 Answers 2

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How to estimate the via pad diameter?

The minimum via pad diameter is given by IPC-2221 in sections 9.1.1 (land requirements) and 9.1.2 (annular ring requirements). For example, for level B class 2 3 fabrication:

$$\text{minimum via pad diameter} = \text{maximum finished hole diameter} + \text{0.35 mm (14 thou)}$$

For example, for a 0.25 mm (10 thou) diameter hole, use a 0.6 mm (24 thou) diameter pad. If you like, you can use a pad diameter larger than the minimum. For example our company uses the following in-house design rule for vias with large holes:

$$\text{via pad diameter} = 1.9 \times \text{ hole diameter}$$

How to decide the via hole diameter?

There are three considerations:

  1. The PCB fabricators minimum and maximum via drill diameter, which are usually listed on their website.
  2. The current carrying capacity of the via. The Saturn PCB Design toolkit incorporates the design rules from IPC-2152, which is the correct standard to use.
  3. For high speed signals you also care about via inductance and via resistance, which the Saturn PCB Design toolkit also gives you.

Please note: According to IPC-6012 Table 3.2, the minimum via plating thickness is 0.02 mm (0.79 thou), however the Saturn PCB Design toolkit uses a default via plating thickness of 0.0254 mm (1 thou). The IPC-6012 number is the correct one to use when calculating the via current carrying capability.

If I am using parallel vias for high currents, will the current divide equally?

In theory, if you have i current distributed over n vias then each via should be sized to handle i / n current. In actuality, more current will pass through the first via it encounters than the last via it encounters. There may be a rule in the IPC standards for this, but I've yet to see it. We use the in-house design rule that every via and trace should be sized with a maximum temperature rise of 10 °C. This gives a conservative number for via hole diameter. This gives use some headroom for cases like this.

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  • \$\begingroup\$ Thanks @C. Dunn for the detailed answer. What about the pi*D = trace width concept? I was not able to relate it with the Saturn PCB toolkit. \$\endgroup\$
    – Andr7
    Feb 2 at 9:29
  • \$\begingroup\$ @Andr7 I am not aware of any IPC or MIL standard that relates via pad diameter to trace width. It's possible that such a rule exists, but I've yet to encounter it. \$\endgroup\$
    – C. Dunn
    Feb 5 at 19:29
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If I am using parallel vias for high currents, will the current divide equally?

Irrespective of the frequency involved the current will not divide equally, anymore than it does with parallel contacts in a connector. You should do your worst case analysis for the number of vias needed, using whatever criteria you care about (temperature rise, voltage drop, ...), then multiply that by 1.25 (or whatever fudge factor you're comfortable with), & round up.

There a couple of Q&A threads on this SE that discuss this is matter.

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  • \$\begingroup\$ "Irrespective of the frequency involved the current will not divide equally" -- why not? \$\endgroup\$
    – anon33
    Feb 1 at 13:23
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    \$\begingroup\$ @anon33 Subject to manufacturing tolerances; plating in deep holes is dubious at best (frankly, it's amazing they can do as well as they do), and vias can always end up stressed or cracked, particularly after soldering, long life with temp cycling, corrosion if applicable, etc. \$\endgroup\$ Feb 1 at 13:53
  • \$\begingroup\$ I suppose I would've written this with a bit more nuance, as contacts are clearly worse in the average case (a few contact points on surface asperities, varying randomly with position, vibration, tension, wear, etc.), and only in the best case do they match the... let's not say average maybe, but median? case for vias. But I think the statistics would work to say average as well. Vias are a solid metal contact up until they crack clean through, and can be intermittent contacts thereafter. Vias are generally quite reliable so this is pretty far down the statistical tail, is the thing. \$\endgroup\$ Feb 1 at 13:55
  • \$\begingroup\$ In any case, such level of analysis is hardly justified, for a quick answer to a lazy question; via sizing and placement has been asked many times here, so a question at this point in time is either very narrow or deep in scope; or poorly researched. And the latter is far more common. \$\endgroup\$ Feb 1 at 13:58
  • \$\begingroup\$ We use the 1.25 fudge factor anytime we are using parallel conductors to handle the current. Contact pins, vias, cable wires, traces on PCBs (though not a much here as it's just as easy to put down a wider trace or use heavier copper). And this is after the relevant derating has been done. \$\endgroup\$
    – SteveSh
    Feb 1 at 14:55

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