This is probably crazy, but: What would happen if I apply a negative voltage between the drain and the gate of a MOSFET (or positive from gate to drain), assuming that this voltage comes from an isolated power supply?
Does the source act as connected to the 0 V plus the "MOSFET diode forward voltage" (let's say 1 V), meaning that Vgs would be around 9 V? And in consequence the MOSFET would be on?
Yes, the MOSFET will be definitively on, at least for any reasonable load currents.
The given transistor has extremely low Rds(on), so unless the load current is very large, Vds will be quickly pulled to zero, thus setting Vgs to a well-defined 10V, putting the transistor in the resistive "on" region.
I suppose a faulted load might deliver enough current to raise questions, but notice in that case, Vgs merely increases in step with Vds, saturating* it harder, at least until Vgs(max) is exceeded and destruction occurs (at which point, the transistor will simply remain on forever).
Also, a fault current might not be considered "reasonable", so there is that. :)
There's also the case where VCC could be negative, and the load current [magnitude] large; here, the body diode limits voltage to -- well, we're talking hundreds of amperes now, and a volt or two drop will similarly lead to destruction within a few seconds, perhaps. But I don't see how the transistor would be anything but "very on" in the scenario (-2V D-S is still +8V G-S).
*I've had enough "FET saturation" nonsense; let "saturation" mean drain voltage saturation, in the consistent way it should've always meant.
As for how it gets there, that's a different problem.
Assuming the transistor, VCC and load are physical objects somewhere, and the "isolated power supply" is a typical mains-powered SMPS, and assuming a typical wiring condition:
The transistor probably blows up, or at least has a good chance to.
We can draw an equivalent circuit like so. To take stock of all effects, we must model the common mode capacitance between the power supply and VCC/GND, and the switching order of both drain and gate connections -- in general, one will mate before the other, and probably multiple times at that (contact bounce).
simulate this circuit – Schematic created using CircuitLab
The inductors are typical of about a half-meter of wiring, and C1, L3 and R2 represents the common-mode, ground-return, or impedance through space between the two power supplies. V3 represents the random common mode voltage between circuits, generally about half the local mains voltage, but it can be more or less -- particularly if the supply has gained an electrostatic charge, or if it's actually common-ground with the other circuit (perhaps through a high resistance, so as not to short it out).
Important variables are the phasing of V3, and the relative timing of SW1 and SW2. I suggest playing around in the simulation. Here is a typical result:
Notice Vgs goes sharply negative, roughly as a divider between C1 (and its initial charge) and M1's Ciss. Depending on which wire connects first, initial Vds, V(C3), etc., this voltage may or may not appear. In general, the transients due to real wiring can be much worse than this, so I would expect the transistor has a good chance of being damaged in practice.
The experiment can be carried out safely if a simple gate protection circuit is added: say, a series 100 ohm resistor, a shunt zener diode from source to gate (say 12V), and another series resistor (at least an ohm) to the gate. (The resistor between zener and MOSFET dampens the LC loop that would otherwise be created, liable to oscillate at 100s of MHz during turn-on.) With a suitable rated zener (zener-type TVS), and a tight layout, this can be done even in the presence of ESD (say the supply is a battery held in hand, carried on top of carpet during a low-humidity winter..).
This is probably crazy, but: What would happen if I apply a negative voltage between the drain and the gate of a MOSFET (or positive from gate to drain), assuming that this voltage comes from an isolated power supply?
The results will be indeterminate and depend on the MOSFET, for any current that is going through the drain the MOSFET would have to be on for it to affect the gate voltage, otherwise the drain will probably be in a high impedance state, so any voltage change on Vgd will be determined by leakage current. This also means that turning on As the gate turns on, the drain voltage will drop from VCC toward GND (source). Since the turning on depends on Vgs and not Vgd this will create problems. If using an isolated supply, make sure the voltage is determined between Vgs and not Vgd.
meaning that the Vgs should be around 9 V ?
No, because the voltage is referenced from the drain and the drain is changing relative to the rest of the circuit, the isolated supply (ground) will change and thus change the gate voltage. You can get switching, it will be somewhat indeterminate and the switching time will be slow, if any reasonable (Amps) amount of current is going through the MOSFET a slow switching time could result in exceeding the power\temperature limit of the package.
