Question
Is it bad design to alter the manufacturer-recommended VQFN footprint as follows:
• Pin copper width: 0.2 [mm] --> 0.3 [mm]
• Pin copper to copper spacing: 0.2 [mm] --> 0.1 [mm]
and if so:
Is it common that standardized IC packages with many pins (QFN, BGA, etcetera) are not be able to achieve standard pricing with a PCB manufacturer?
Background
• Package: VQFN
I want to manufacturer a board with a VQFN package.
The package pins have:
- Pin copper width: 0.2 [mm]
- Pin copper to copper spacing: 0.2 [mm]
• PCB Manufacturer: PCBWay
PCBWay's capabilities specify SMT pin copper width as:
Normal cost ≥ 12 [mil] = 0.30 [mm] Medium cost ≥ 09 [mil] = 0.23 [mm] High cost ≤ 09 [mil]
• IPC-2221B
IPC-2221B specifies minimum copper spacing (under 15 [V] ) as 0.1 [mm]:
• Package: BGA
The IC has an alternative package as a BGA, but:
- It is not compliant, like VQFN
- Copper pad width/spacing is better remedied than VQFN, after alteration (shown below)
- Via pad diameter appears to make this impossible (shown below).
- It is costlier
- The thermal properties are significantly worse due to the smaller package size.
After pin copper width/spacing alterations, the copper to copper spacing is much better than the VQFN:
• Pin center to center: 0.50 [mm]
• Pin copper width: 0.25 [mm] --> 0.30 [mm]
• Pin copper to copper spacing: 0.25 [mm] --> 0.20 [mm]
BGA will ultimately require Via In Pad to trace the inner pins past the outer pins.
PCBWay's associated capabilities here are:
Drill diameter minimum : 0.20 [mm] ( @ board thickness ≤ 1.6 [mm] )
Minimum weld ring (outer layer) : 5 [mil] = 0.1270 [mm] (@ Cu Thick : 35 [µm] = 1 [oz/ft^2] )
Thus:
Minimum via pad diameter = (0.20 + 2 • 0.127) [mm] = 0.454 [mm]
This leaves (0.500 - 0.454) [mm] = 0.046 [mm] between copper pads, at best.
Unfortunately, this is also not compliant and BGA is therefore not an option.
