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I am asked to find the gain A for this negative feedback circuit below:

enter image description here

enter image description here

(A: gain, G: all of the gain of the circuit, F: return ratio)

The simplified circuit above shows the gain A that I am trying to find.

I know that if this circuit had only one FET A = Vo/Vi=-gm*Rl. However, I just can't figure out how the gain A would change, if we were to add two additional FETs to the circuit. Any help would be appreciated.

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2 Answers 2

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By your own statement, each FET stage will have voltage gain:

$$ A_1 = A_2 = A_3 = -g_mR_L $$

Each stage multiplies the voltage output of the previous stage, so if the first stage FET has gate voltage \$V_{G1}\$, the second gate is \$V_{G2}\$ etc., then you have:

$$ \begin{aligned} V_{G2} &= A_1V_{G1} \\ \\ V_{G3} &= A_2V_{G2} \\ \\ V_{O} &= A_3V_{G3} \\ \\ &= A_3(A_2V_{G2}) \\ \\ &= A_3(A_2(A_1V_{G1})) \\ \\ &= (-g_mR_L)^3V_{G1} \\ \\ \\ A &= \frac{V_O}{V_{G1}} \\ \\ &= (-g_mR_L)^3 \end{aligned} $$

This number is negative (due to the odd number of stages), and is assumed to be huge. The circuit is functionally similar to the classic inverting amplifier employing an op-amp:

schematic

simulate this circuit – Schematic created using CircuitLab

No doubt you are familiar with the closed loop gain \$G\$ of such a system:

$$ G = \frac{V_{OUT}}{V_{IN}} = -\frac{R_F}{R_S} $$

Interestingly, this is independent of \$A\$, which I'll touch upon below.

In your second circuit, the system is represented as a modular block diagram, where feedback is shown to be added to the original input.

Note: For feedback to be negative, one of the following conditions is necessary: gain \$A\$ should be negative, feedback factor \$F\$ should be negative, or the addition should actually be a subtraction. That diagram has none of those conditions, so feedback is positive, and the system is unstable. I have to assume this is an oversight on the author's part, somewhere there is a negation, and the author intended that feedback be negative.

In my op-amp circuit above, feedback is negative because the op-amp performs a subtraction of some fraction of the output, as indicated by the '−' symbol at the input terminal where feedback is applied.

In your first circuit, with the cascaded FET stages, feedback is also negative, because there are an odd number of individual negative-gain stages. Total gain from \$V_{G1}\$ to \$V_O\$ is therefore negative.

Anyway, the behaviour of a negative feedback system such as the one (almost) depicted in your second diagram, is well documented, and has this closed-loop gain:

$$ \frac{v_{OUT}}{v_{IN}} = \frac{A}{1+AF} $$

Note that I've used lower-case \$v\$, suggesting that \$v\$ is referring to amplitude of some AC signal, rather than potential at any particular instant in time.

If gain \$A\$ is large enough, this becomes a very close approximation to:

$$ \frac{v_{OUT}}{v_{IN}} = \lim_{A\rightarrow\infty}{\frac{A}{1+AF}} = \frac{1}{F} $$

I think that this exercise is designed to consolidate all these facts into a better understanding of:

  • Many cascaded stages leads to very large open-loop gain \$A\$, which in a closed loop will result in a lower but precisely controllable gain: $$ \frac{v_{OUT}}{v_{IN}} = \frac{1}{F} $$
    This is independent of open-loop gain \$A\$, but does rely on \$A\$ being very large.

  • The circuit with FET stages, and feedback and input resistances, closely resembles, and is functionally equivalent to, the classic inverting amplifier employing an op-amp, and has the same gain equation: $$ \frac{V_{OUT}}{V_{IN}} = -\frac{R_F}{R_S} $$

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Re-draw the schematic, using voltage controlled voltage sources as FET models. The voltage controlled voltage source (VCVS) G is an only component of the hybrid-pi model, a small-signal FET model, in which the output resistance is infinite and therefore can be omitted in the model. As you do not specify output resistance in your post, you are defaulting its value to infinity.

threestageamp

Examining the plot of a transient simulation you can easily verify that the stage gains are indeed multiplied. With gm=0.1 and RL=1000 the stage gain is 100, with three stages the total gain (open-loop gain of all three stages connected in series) is 1E+06, and the circuit closed-loop gain approaches a value of -Rf/Rs, independent of gm and RL, as if the circuit is an ideal operational amplifier.

What is more important for your problem, it is that the overall stage gain in this circuit is exactly factorized (expressed via a product of stage gains), as the inputs of stages do not load outputs (the input resistance of VCVS is infinite) and there are no internal feedbacks in the circuit.

Yes, the exact gain value does depend on gm and RL. And this model can be used not only for SPICE simulation, but, thanks to its factorization property, it simplifies symbolic calculations and helps you to arrive at an exact formula for the closed-loop gain, too. Because it is homework, do it!

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  • \$\begingroup\$ A story about this post. Noticed this question early. The question was candidly tagged "homework", but it looked as if the OP knows better, so a long while I just watched the community reaction. To my surprize, nobody'd requested "Datasheets, please" neither criticized the circuit drawing style or the other typical reaction of a certain SE 'experts'. Assuming the question is written in good faith, I ventured to write an answer covering maximum possible to be communicated to a struggling student short of directly doing their homework. \$\endgroup\$
    – V.V.T
    Feb 5 at 5:15
  • \$\begingroup\$ Later, another answer appears, looking as if the other student did the same homework and (mistakenly) turned their paper in to electronics.SE instead of their professor. Now, in my opinion, this post with its two answers embodies a good example of what has to be encouraged and what are not recommended practices while answering 'homework' questions. Regardless of whether there is any truth in my interpretation of intentions of other participants when writing their contributions, kudos to them for helping me streamline my understanding of SE's policies applicable to 'homework'-tagged questions! \$\endgroup\$
    – V.V.T
    Feb 5 at 5:16

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