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I need to initialize multiple lookup tables, for which I need a 12-bit array of possibly many indexes. An example:

reg [11:0] address[1:0];

For this, how do I initialize it with 0? For all index values? Also, I am unable to use the initial block, since it cannot be used in RTL synthesis. The purpose of this is to interface multiple lookup tables and access the values via an index through the address variable.

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  • \$\begingroup\$ This is probably specific to the Xilinx FPGA tool suite you are using. Did you have problems when you tried the recommendations in the documentation? You should add more details to the question. \$\endgroup\$
    – toolic
    Commented Feb 6 at 12:48
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    \$\begingroup\$ Where did you get the idea that initial blocks were not supported for synthesis? The Xilinx documentation shows otherwise for this particular case in the Vivado & ISE documentation. Its probably better to say that initial blocks are generally not supported for synthesis, however RAM & ROM initialization are implemented using initial blocks for Xilinx syntheses according to Xilinx, which is constant with my experience FWIW. \$\endgroup\$
    – Mikef
    Commented Feb 6 at 14:55
  • \$\begingroup\$ @Mikef I was learning verilog, and I learnt that as a property of the Initial block. \$\endgroup\$
    – DaveFenner
    Commented Feb 7 at 4:49

1 Answer 1

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The question refers to a look-up table, which is a ROM. These solutions apply to both RAM and ROM models.

There are 2-3 good ways to perform ROM/RAM initialization in Vivado & ISE for Verilog.

For Vivado, refer to Xilinx doc UG-901 Specifying-RAM-Initial-Contents-in-the-HDL-Source-Code

Two styles are shown in the guide:

  1. for loop
reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];    

integer i;    
initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;
end 

2 Using an external data file

Use the file read function in the HDL source code to load the RAM initial contents from an external data file.
The external data file is an ASCII text file with any name.
Each line in the external data file describes the initial content at an address position in the RAM.
There must be as many lines in the external data file as there are rows in the RAM array. An insufficient number of lines is flagged.
The addressable position related to a given line is defined by the direction of the primary range of the signal modeling the RAM.
You can represent RAM content in either binary or hexadecimal. You cannot mix both.
The external data file cannot contain any other content, such as comments.

reg [31:0] ram [0:3];

initial begin
$readmemb("rams_20c.data", ram, 0, 3);
end                                

The following external data file initializes an 4 x 32-bit RAM with binary values:

00001110110000011001111011000110
00101011001011010101001000100011
01110100010100011000011100001111
01000001010000100101001110010100

Another way to create ROMS with initialization using Vivado
The Vivado IP Catalog tool allows the user to launch a block memory generator to create custom ROMS blk_mem_gen_ds512 See the section with the heading 'Specifying Initial Memory Contents' where it is stated
"The Block Memory Generator core supports memory initialization using a memory coefficient (COE) file or the default data option in the CORE Generator GUI, or a combination of both."

Xilinx ISE has known bugs with $readmem<h/b>()
You could use approach 1. or use the ISE Coregen tool to create the RAM or ROM and choose to create an initialization file when creating the core.

ISE support stopped years ago; its difficult to find documentation (today, when searching for ISE docs you find are broken links pointing to the Xilinx/AMD site, it looks like they don't what users reading the old docs). I did find this guide which walks the user thru the process of creating memories (with init files) using the ISE Coregen tool. rose-hulman

Another way for ISE I found a guide for the ISE synthesis tool XST here cse372-Spring06 from 2006 which shows this style

reg [19:0] ram [63:0];
initial begin
 ram[63] = 20'h0200A; ram[62] = 20'h00300; ram[61] = 20'h08101;
 ram[60] = 20'h04000; ram[59] = 20'h08601; ram[58] = 20'h0233A;
 ...
ram[2] = 20'h02341; ram[1] = 20'h08201; ram[0] = 20'h0400D;
end
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  • \$\begingroup\$ Thank you! I got it. About the initial block, I guess it's not allowed, but for RAM/ROM initialization as you said, I must have missed it somehow. \$\endgroup\$
    – DaveFenner
    Commented Feb 7 at 5:14
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    \$\begingroup\$ Xilinx UG-901 Synthesis Guide is your friend \$\endgroup\$
    – Mikef
    Commented Feb 7 at 13:31
  • \$\begingroup\$ @DaveFenner did you encounter a related issue? \$\endgroup\$
    – Mikef
    Commented Mar 29 at 14:13
  • \$\begingroup\$ No, not yet. I just missed seeing this comment when I had initially posted the question. Thanks though! Edit: I must've unchecked the question by mistake: Just noticed. \$\endgroup\$
    – DaveFenner
    Commented Mar 29 at 16:07

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