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I don't have encryption licenses for Vivado or Quartus to encrypt my Verilog/VHDL modules and so I cannot give my RTL to any user. I don't want to give out synthesized netlists but only encrypted RTL.

What are the ways to encrypt a Verilog/VHDL module (any opensource or 3rd party encryption) such that encrypted RTL can be synthesized by Vivado and Quartus?

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With IEEE-1735, private key is only needed for decrypting files. Anyone with the relevant public keys can encrypt its IP to target a specific tool.

Synthesis/simulation tools vendors usually have a set of key pairs per product.

When you encrypt a HDL file, you need to target a set of supported synthesis/simulation products, and use their public keys as an input to the encryption tool.

As most tools supporting the standard are publicly available as software-only, they need to have private keys stored somewhere in the code, more or less obfuscated. There are periodic leaks of said keys.

There are some available tools for encrypting with IEEE-1735 available publicly. You have to gather the public keys from vendors you want to target. Xilinx has documentation for this, for instance.

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  • \$\begingroup\$ What are the tools available publicly? \$\endgroup\$
    – Im Groot
    Feb 11 at 15:43
  • \$\begingroup\$ Vivado's, IPEncrypter's (not endorsing any of them, I never used them) \$\endgroup\$
    – Nipo
    Feb 12 at 9:00

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