# What is an intuitive explanation for why the power supply in this MOSFET circuit does not affect the output voltage?

Consider the following circuit

Let's name the top MOSFET m1 and the bottom one m2 for brevity.

Assume that both MOSFETs operate in the saturation region. $$\L_1,W_1\$$ are the dimensions of the n-channel of m1, and likewise for m2.

Now, on autopilot, I would write

$$i_{DS_1}=K_n\frac{W_1}{L_1}(V_A-V_{OUT}-V_T)^2\tag{1}$$

$$i_{DS_2}=K_n\frac{W_2}{L_2}(V_B-V_T)^2\tag{2}$$

I would then equate and solve for $$\V_{OUT}\$$

$$V_{OUT}=V_A-V_T-\sqrt{\frac{L_1W_2}{L_2W_1}(V_B-V_T)^2}\tag{3}$$

I say autopilot because though I know how to do such calculations, I don't have a good feel for what is really happening.

Let me try to reason about what would happen if we tried to actually build this circuit.

1. I would get three voltage sources. They would provide $$\V_A\$$, $$\V_B\$$, and $$\V_S\$$. The important thing is that these variables are under my direct control.

2. I would choose the MOSFETs. Assume I can pick out MOSFETs with any dimensions of the $$\n\$$-channel, that is any $$\L\$$ and $$\W\$$ and assume that $$\V_T\$$, the threshold voltage for the MOSFETs is always $$\\mathrm{1V}\$$.

3. Because I want the MOSFETs to be in saturation, I must choose $$\V_A\$$, $$\V_B\$$, $$\V_S\$$, $$\L_1\$$, $$\L_2\$$, $$\W_1\$$, and $$\W_2\$$ such that the conditions for saturation are satisfied. They are

$$V_S-V_{OUT}\geq V_A-V_{OUT}-V_T\geq 0$$

$$\implies V_S\geq V_A-V_T\geq V_{OUT}$$

and

$$V_{OUT}\geq V_B-V_T\geq 0$$

Now, $$\V_{OUT}\$$ is given by (3) assuming saturation of both MOSFETs.

1. I connect the circuit elements as in the diagram.

Let me try to go through such an exercise.

Suppose I set $$\L_1=L_2=W_1=W_2=1\$$.

Then $$\V_{OUT}=V_A-V_B\$$.

Next, say I select $$\V_B=\mathrm{4V}\$$.

Since I need to have $$\V_{OUT}\geq V_B-V_T=\mathrm{3V}\$$ and since $$\V_{OUT}=V_A-V_B\$$ then $$\V_A\$$ needs to be at least $$\\mathrm{7V}\$$.

Suppose it is $$\\mathrm{7V}\$$.

Finally, to satisfy the saturation condition for m1 we must have $$\V_S\geq V_A-V_T\geq V_{OUT}\$$, that is $$\V_S\geq \mathrm{6V\geq 3V}\$$ so I can pick a $$\V_S\geq\mathrm{6V}\$$.

Now, for some reason, $$\V_{OUT}\$$ does not depend on $$\V_S\$$. If I choose a $$\V_S\$$ of 1000V it seems like it doesn't affect anything. Why is this so?

## 2 Answers

Now, for some reason, VOUT does not depend on VS. If I choose a VS of 1000V it seems like it doesn't affect anything. Why is this so?

Assuming that both MOSFETs are N channel and, that they are placed into your circuit with the source on the lower pin then, the upper MOSFET (M1) is connected as a source follower.

Basically, a source follower does what it says on the tin; the source "follows" the gate so, if you have (say) 10 volts on the gate (Va), the source will be no more than around 8 volts. The 2 volts difference is needed to achieve the gate threshold voltage (a hand wavy estimation).

And, it is largely independent of the supply voltage Vs providing Vs is greater than Va. Think about what an N channel MOSFET needs to operate correctly; the source has to be less than the gate for the channel to start to become conductive.

What is an intuitive explanation for why the power supply in this MOSFET circuit does not affect the output voltage?

Hopefully, that's intuitive enough.

The intuitive reason is that if the source of a FET is not held at some fixed potential, and is instead allowed to vary (by placing a resistor there, for example), then source potential tends to "follow" the gate, as gate potential varies. Such a configuration is called a "source follower". Unless gate potential exceeds the drain, the relationship is:

$$V_S \approx V_G - V_{GS(TH)}$$

Here source potential is $$\V_S\$$, gate is $$\V_G\$$, and $$\V_{GS(TH)}\$$ is the FET's threshold gate-source potential difference.

In that relationship, there's no mention, or dependence upon, drain potential. That's why you don't see it in your result either.

If you want to know why, then read on.

From now on, I want to avoid using the letters S, G and D in variable names, to avoid conflict with the names you've chosen in your example. Instead my supply is potential is $$\V_X\$$, gate potential is $$\V_{Y}\$$, and source potential $$\V_Z\$$:

simulate this circuit – Schematic created using CircuitLab

The state of conduction of a FET's channel (between drain and source) is controlled by the potential difference between its gate and source. That potential difference is referred to as $$\V_{GS}\$$, which in my schematic above would be:

$$V_{GS} = V_Y - V_Z$$

The "threshold voltage" is a value for which the FET just begins to conduct, usually denoted $$\V_{GS(TH)}\$$, and for an N-channel device would be positive. For an N-channel device, if one applies a potential difference between gate and source that exceeds $$\V_{GS(TH)}\$$, so that $$\V_{GS} > V_{GS(TH)}\$$, the channel will become more conductive, and vice versa.

For this exercise, let's assume $$\V_{GS(TH)} \approx 2V\$$.

Now consider what happens when I apply a potential $$\V_Y = +10V\$$ to the gate, as is the case for M1 above left. Initially, with no channel current flowing, the voltage across R1 is 0V, and source potential $$\V_Z=0V\$$. That gives us:

\begin{aligned} V_{GS} &= V_Y - V_Z \\ \\ &= (+10V) - (0V) \\ \\ &= +10V \end{aligned}

Remembering that $$\V_{GS(TH)} \approx 2V\$$, clearly $$\V_{GS} > V_{GS(TH)}\$$. Therefore the FET's channel is very conductive in this state, and current will rapidly rise. Consequently, the voltage across R1 rises, and source potential $$\V_Z\$$ rises with it.

If $$\V_Z\$$ rises too far, for instance it reaches +11V, then we have this situation:

\begin{aligned} V_{GS} &= V_Y - V_Z \\ \\ &= (+10V) - (+11V) \\ \\ &= -1V \end{aligned}

This is far less than $$\V_{GS(TH)}\$$, and the FET channel will stop conducting. Channel current must fall, and source potential $$\V_Z\$$ must also fall.

In between those two conditions, there is a point at which source potential $$\V_Z\$$ is exactly the right value to produce the condition $$\V_{GS} \approx V_{GS(TH)}\$$. At that point the channel is conductive enough to pass exactly the right current, to produce exactly the right voltage across R1, and an equilibrium is established.

If channel current were then to rise even a tiny bit, that would raise $$\V_Z\$$, reducing $$\V_{GS}\$$, switching the FET off very slightly, reducing current and restoring the equilibrium.

Similarly, if channel current were to fall slightly, $$\V_Z\$$ would also fall, this time increasing $$\V_{GS}\$$ and channel conductivity, restoring current to whatever it was before.

In other words, whatever perturbations occur at the FET's source, the FET immediately responds to counter those perturbations, maintaining a fixed potential there. There is a state of equilibrium, able to correct and maintain itself due to an inherent negative feedback.

This state of equilibrium is when $$\V_{GS} = V_Y - V_Z = V_{GS(TH)}\$$. That can be written:

\begin{aligned} V_Y - V_Z &= V_{GS(TH)} \\ \\ V_Z &= V_Y - V_{GS(TH)} \\ \\ \end{aligned}

This is saying that $$\V_Z\$$ "follows" $$\V_Y\$$, but is always slightly lower by amount $$\V_{GS(TH)}\$$. Hence the name "source follower", also called "common drain". Above right you see I've increased gate potential $$\V_Y\$$ by 10V, and the source has also increased by the same amount, always maintaining the condition

$$V_Z = V_Y - V_{GS(TH)}$$

Here's a plot of $$\V_Z\$$ versus $$\V_Y\$$ as I sweep $$\V_Y\$$ from 0V to +30V:

This "following" action is clearly visible, except when $$\V_Y < V_{GS(TH)}\$$ or $$\V_Y > V_X + V_{GS(TH)}\$$. The FET's source is unable to wander outside the minimum and maximum potentials imposed by the supplies.

In the relationship $$\V_Z = V_Y - V_{GS(TH)}\$$, there is no mention of supply (drain) potential $$\V_X\$$ anywhere. The only time when $$\V_X\$$ plays a role is during the condition $$\V_Y > V_X + V_{GS(TH)}\$$.

In your circuit you don't have a resistor in the source path, but the transistor's behaviour will remain the same; it will be a "source follower" as long as the effective resistance of whatever is connected at the source is positive, and not so small as to compete with the FET's own minimum channel resistance.