# Double Pulse Schematic

I had a doubt in the schematic of the gate driver part of the following double pulse test circuit. Do I need to connect the source pin of Q2 to VDDB? What will be the path of the current during ON and OFF?

Do I need to connect the source pin of Q2 to VDDB?

Longer answer: Doing this connection would connect pins 1 & 2 of J3 across R3. I suspect R3 is a very low-value resistor (its value is not shown on your schematic) used to monitor the current through Q2. I suspect J3 provides power to the gate driver within U, so this would simply place a heavy load across that power supply.

What will be the path of the current during ON and OFF?

In the unlikely event that the power supply at J3 can supply the load current in R3 to maintain its output voltage at, say +12VDC, then all that you would have done is connect Q2 source to +12V. In which case, Q2 would never turn on, since its gate-to-source voltage never goes above 0V.

If you do this connection, the most likely outcome will be one of two possibilities:

1. the power supply connected to J3 will go into current limit.
2. R3 will burn up (it is most likely only rated to drop, say, 1V across itself).

• Thanks Fabio! What about connecting Q2 source to GND_HV ? Will it affect my drain current measurement? Feb 12 at 8:27
• Q2 source is already connected to GND_HV via R3. This allows source current to be measured (observed with a scope) via the voltage at TP2. Note that the source current also includes the gate drive current in addition to the drain current. If you want to see just the drain current, then you may have to consider connecting the Q2 source to the VSSB of U1 and disconnecting the link between C5 and GND_HV. In other words, you must try to force the current in R3 to only be the source current without the gate current returning to U1. Feb 13 at 0:43