I generated +/-5V 1MHz square wave signal from D-flipflop (part number:CD4013).i planned to use the signal as an excitation for LC tank(L:47uH C:500-1000pF) through a coupling capacitor.I planned to reduce the swing of square wave with voltage divider between signal out of logic gate and the ground(0V)(two equal resistance) at output,but problem is ,the output is not as expected. The following are the results with corresponding resistor values. 10Kohm - +/-1.3 V--- 1Kohm - +/-0.4V---- 100kohm - +/- 0.3V

LC oscillator is not connected just the output is probed at mid point of divider.

Is the load impedance a problem when the output of CMOS gate directly fed into voltage divider. if so 100kohm should produce a larger swing but it didn't,source and sink capabilities of CMOS at 10V input is -2.6 and +2.6 mA .what might be the problem and what is the correct way to attenuate the CMOS logic output

I planned to use this method as the square wave is fed just for topping up once the LC tank is in resonance.Drive speed consideration are not taken as it is not for driving other logic input,planned a divider with 10k resistor,as the output voltage was not correct tried other combinations

Update: The above mentioned measurent were taken 1MOhm probe impedance,changed to 10Mohm obtained values as follows 10Kohm - +/-3.44 V--- 1Kohm - +/- 3V---- 100kohm - +/- 1.44V

Update: Sorry to all members,one of scope probe is broken,seemed to work well till yesterday,so the issue is only with the probe,it is attenuating voltage randomly,checked with the other probe,divider output is okay.thought ahead of myself and posted the question,regret for the mistake.

And the faulty probe was showing the DC voltages correctly that is where I got confused,and didn't suspected it.my guess is must be impedance mismatch.

  • \$\begingroup\$ How can you get a negative voltage from your D type flip flop. State the actual peak levels with 0 volts as your reference. Please also unambiguously show where the output is that you refer to. Best remedy is do a schematic. Have you tried simulating your set-up? \$\endgroup\$
    – Andy aka
    Commented Feb 12 at 9:15
  • \$\begingroup\$ @Andyaka sorry..I will present it clearly CD4013 supply is +/5V so output swings +/-5V with reference to gnd(0V).voltage divider is connected between output of flip flop(Q output ) and gnd(0V).desired signal is probed between middle of voltage divider and gnd(0V).currently laptop is not availlable so can't provide schematics,sorry for inconvenience.i stated peak-peak in the question if actual peak then it has to be the Max positive swing. \$\endgroup\$
    – dhuwarkesh
    Commented Feb 12 at 9:34
  • 1
    \$\begingroup\$ I’m voting to close this question because OP states "This is question due to misinterpretation of faulty scope probe.closing it." \$\endgroup\$ Commented Apr 20 at 13:38

1 Answer 1


This is question due to misinterpretation of faulty scope probe.closing it.

  • \$\begingroup\$ Thanks for coming back with a resolution. \$\endgroup\$
    – greybeard
    Commented Apr 20 at 13:06

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