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I’m following a guide (Here is the link to the guide: https://www.hackster.io/whitney-knitter/dsp-for-fpga-using-xilinx-dds-with-custom-fir-f82447) for implementing a custom FIR filter in Vivado and encountered a discrepancy between my approach and the guide, particularly regarding signal types and simulation initiation. The guide doesn't appear to use inout signals or wire types in the testbench, which contrasts with my current setup where Vivado generated a wrapper (design_1_wrapper) with inout ports, necessitating wire types for connection.

Goal: Understand how to initiate simulation for a custom FIR filter design accurately, mirroring the guide's approach without explicitly using inout signals in the testbench.

Issue: My simulation setup involves inout ports, leading to complications not evident in the guide. Specifically, the guide's testbench directly uses reg types for clock and reset signals:

fir_design fir_design_i(
    .clk(clk),
    .reset(reset)
);

However, in my wrapper (design_1_wrapper), generated by Vivado, I find only inout ports, which has led me to use wire types due to Vivado's inout signal requirements with strange names like FIXED_IO_ps_clk, FIXED_IO_ps_porb did she just rename those? :

design_1_wrapper design_1_i(
    .FIXED_IO_ps_clk(tb_clk),
    .FIXED_IO_ps_porb(tb_reset)
);

This adjustment has introduced errors and confusion about the correct simulation setup.

Questions:

How does the guide initiate simulation without addressing inout signals, and how can I replicate this in my setup? Could the issue stem from my selection of the top module or the way I've generated the wrapper? How should the top module or wrapper be configured to avoid complications with inout signals for simulation (if that was the problem)?

Attempts & Issues:

I've closely followed the guide for implementing a custom FIR filter in Vivado. However, my simulation doesn't start as expected due to inout ports in the auto-generated wrapper, which contrasts with the guide's direct use of reg types for clock and reset. Following toolic's advice, I tried connecting inout ports to wire types, driven by reg signals, but encountered errors: [VRFC 10-426] cannot find port reset on this module [VRFC 10-2063] Module <design_1> not found... I'm puzzled by how the guide initiates simulation without these inout issues. Could my problem be related to the top module selection or wrapper generation? Insights or clarifications on aligning my setup with the guide would be invaluable.

Understanding the guide's methodology for simulation initiation and how it avoids complexities with inout signals would greatly assist me in progressing with my project. Any insights or clarifications would be immensely appreciated.

update: Thank you for the guidance, @toolic. Based on your advice, I've updated my original question with a simplified version of my issue to make it more clear and self-contained. I hope this helps in providing any further insights you might have.

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1 Answer 1

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You should connect the inout ports to signals declared as wire, then drive the wires from the signals declared as reg. Here is a self-contained example:

module design_1_wrapper (inout FIXED_IO_ps_clk, FIXED_IO_ps_porb);
endmodule

module tb;

reg  tb_clk, tb_reset;

wire io_clk   = tb_clk;
wire io_reset = tb_reset;

design_1_wrapper design_1_i (
    .FIXED_IO_ps_clk (io_clk),
    .FIXED_IO_ps_porb(io_reset)
);

always #5 tb_clk = ~tb_clk;

initial begin
    tb_clk = 0;
    tb_reset = 0;
    #40;
    tb_reset = 1;
    #500 $finish;
end

endmodule

When a design has an inout port, the testbench typically will have one reg and one wire for that port.

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  • \$\begingroup\$ Hello, Thank you for your prompt reply. Unfortunately, I'm still encountering errors despite closely following the instructions provided in the guide. I'm at a loss trying to understand how the simulation is initiated as per the guide using the specified code. The errors I'm encountering are as follows: <code>[VRFC 10-426] cannot find port reset on this module<code> <code>[VRFC 10-2063] Module <design_1> not found while processing module instance <design_1_i><code> Could you please provide some guidance on how to resolve these issues? I'm eager to get the simulation running as intended. \$\endgroup\$ Commented Feb 14 at 17:10
  • \$\begingroup\$ @Stuck_Between_Pixels: You're welcome. Add all new information into the question, instead of in the comments. As you can see, you can't easily format comments. Keep in mind that there is a lot of setup associated with what you are trying to accomplish. Try to narrow your question down to something that others can easily reproduce. This is why I created the self-contained code to demonstrate that using inout ports can work. That was my way to provide "Any insights or guidance", as requested. \$\endgroup\$
    – toolic
    Commented Feb 14 at 17:32

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