For a passively-cooled portable device (fanless, ambient cooling), what are typical methods to supplement the thermal pad of an IC to mitigate device temperature rise, (beyond efficient operation of the device)?

Presumed Focus Areas [Modified By Feedback Below]

  • Will increasing the surface area of the back-layer pad (without proportionally increasing the surface area of the front layer pad or proportionally adding thermal vias) improve thermal conditions?

(Increasing the surface area of the front-layer pad is precluded by the density of the traces and vias from the surrounding pins.)


  • For a (many) multilayer board, will replicating the front-layer pad on the internal layers beneath it and the back-layer pad further improve thermal conditions?

These pads do not connect to larger area planes (if they did; they would definitely be beneficial).


TI's RRF package (depicted below; VQFN, 76 pins) calls for a thermal pad and thermal vias beneath its body, on the front-layer of the board. Further beneath that, the back-layer of the board should have an identical pad which receives the thermal vias (via solid connections).

  • Replicate this thermal pad on all internal layers to supplement the back-layer pad?

enter image description here


Linked questions


1 Answer 1


An interesting article, by Douglas Brooks and Johannes Adam, about modeling thermal vias concludes that copper area is the most helpful in removing heat. Number of thermal vias is of little benefit as can be seen in Figure 2 from the article which is shown below.

enter image description here

This is for a 1.6 mm thick FR4 board measuring 100 mm on a side, heated area which is the same size as the 25 x 25 mm2 small plane, large plane is the size of the board. Via diameter is 0.3 mm (apx 12 mil) filled with solid copper. Near plane is 300 um (apx 12 mil) below the surface.

Hence, having a large plane is very beneficial for thermal considerations.

  • \$\begingroup\$ Where is the ultimate heat sink in this design? Is it air being blown over the board? Edge cooled? \$\endgroup\$
    – SteveSh
    Feb 14 at 17:50
  • 1
    \$\begingroup\$ @SteveSh naturally cooled to surrounding air, no forced air cooling. There is the 20° heat sink simulation which places a heatsink on the backside of the board. Read the article, it's interesting. \$\endgroup\$
    – qrk
    Feb 14 at 17:57
  • \$\begingroup\$ Interesting article, one I hadn't seen. As a counter example, one of our recent designs, a SMPS 10 layer SMT board with 2 oz copper layers, the thermal analysis showed the need for thermal vias under many of the power FETs. \$\endgroup\$
    – SteveSh
    Feb 15 at 2:54
  • \$\begingroup\$ Per the link, the copper-connected copper plane on the back-layer will be an improvement; marginal if the same size as the IC and much improved if much larger. What is less clear is whether supplementing the back layer pad of any size with front-layer-sized copper pads on the internal layers between the front-layer pad and back-layer pad would be at all beneficial. \$\endgroup\$
    – kando
    Feb 15 at 18:02
  • \$\begingroup\$ (For clarity, these front-layer sized pads on the internal layers would not connect to a greater internal-layer plane.) \$\endgroup\$
    – kando
    Feb 15 at 18:08

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