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So im learning the SAP 1 Computer Architecture. Most things I get pretty well, but from what I understand: (Lets pretend it's an 8bit and address is 4 bits and opcode is 4bit) http://www.instructables.com/id/How-to-Build-an-8-Bit-Computer/step8/Program-Memory-and-RAM/

^^ is the guide im? kinda going through)

The Program Counter gets the next ADDRESS for the program which it STORES in the MAR (Memory Address Register), (So the last 4 bits), so MAR only needs to be capable of holding 4 bits(1/2 byte) correct? (Or does the MAR store an entire byte......)

It then stores this in RAM (via a multiplexer), in the guide here 16 bytes, so the multiplexer chooses what Address it will be stored at. (Is it storing 4 bits or 8 bits.....It seems like it'd only store the 4 bits from the MAR). If so....why does the RAM even exist? Couldn't the MAR just store everything. But the Website above shows the RAM outputting 8 bits?

From there the Instruction Register is storing the 4 bits of ADDRESS and then the 4 bits of the OPCODE Correct? So the 4 OPcode bits go into the Control Matrix which tells it what to do and the other 4 bits (the address) go where? Whats the point of the 4 ADDRESS bits? Whats our next step?

Would it go into the Accumulator? What for?

As you can tell im a bit stuck at what happens next? I really want to understand this but im just stuck.

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    \$\begingroup\$ Didn't read the entire instructable, but I'm under the impression that it uses some four bit wide logic to make an 8 bit CPU from it. That is not a generic CPU architecture. \$\endgroup\$ – jippie May 22 '13 at 19:57
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That instructable is kind of confusing. You'd be better off selecting an actual book from the big list.

Without getting into a discussion on various architectures which would just lead down the rabbit hole, I'll use the architecture described in the instructable and work through an example of a simple addition program.

Below is the RAM as described. On the left are the 16 addresses. Each address holds a byte. This byte may be data (demarcated as D) or an instruction consisting of an opcode (O) and an address (A).

1111 DDDDDDDD
1110 DDDDDDDD
1101 DDDDDDDD
1100 DDDDDDDD
1011 DDDDDDDD
1010 DDDDDDDD
1001 DDDDDDDD
1000 DDDDDDDD
0111 OOOOAAAA
0110 OOOOAAAA
0101 OOOOAAAA
0100 OOOOAAAA
0011 OOOOAAAA
0010 OOOOAAAA
0001 OOOOAAAA
0000 OOOOAAAA

The program counter (PC) starts off at zero. This tells the processor to fetch the byte at address 0000 from the RAM and treat it as an instruction. So the processor fetches the byte into the Instruction Register (IR). The top four bits of the data retrieved go to the "control matrix" and the bottom four to the MAR. This split happens each time an instruction is fetched.

Note: Those particular terms are not what I would consider typical (at least in my experience) but we'll go with them for this example.

The processor fetches the instruction at address 0000 since PC = 0000. Our first opcode is going to say, "move the data that is in address 1000 into the accumulator" (I'm going to use prose instead of confusing things by picking a particular flavor of assembly language).

So the processor fetches the data at address 1000 (let us say it is the number 2) and moves it into the accumulator (ACC). Now ACC = 2. The program counter gets automatically incremented so PC = 0001.

The next instruction at address 0001 says, "add the data that is in the accumulator to the data at address 1001 and store it back in the accumulator". So the processor takes what is in the accumulator and feeds it into one side of the Arithmetic Logic Unit (ALU). The processor takes the data that is at address 1001 (let us say it is the number 3) and feeds it into the other half of the ALU. The ALU preforms the addition of the two numbers and the output (the number 5) is stored in the accumulator. Now ACC = 5. The program counter again gets automatically incremented so PC = 0010.

The last instruction of our little program at address 0010 says, "store what is in the accumulator at address 1010". The processor then takes what is in the accumulator and stores it at address 1010. So now RAM address 1010 = 5.

Hopefully that example is a bit clearer picture of what is going on. Various architectures handles things slightly different ways. But the basic flow is usually similar.

Below is diagram of the basic registers and control circuits of most processors. There are a few more registers than we've been discussing. You can ignore those for the moment for the purposes of this discussion or read more about them at your leisure. Hopefully the visual aid will help make things a bit clearer.

CPU diagram

Below is the flow of each step a processor takes. First it fetches an instruction and then that instruction tells it to fetch data to operate on from RAM.

Step 1. [Address]        PC  -> MAR -> RAM  
Step 2. [Instruction]    RAM -> MDR -> IR  
Step 3. [Address]        IR  -> MAR -> RAM  
Step 4. [Data]           RAM -> MDR -> ACC (or R0, etc.)  
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  • \$\begingroup\$ Once the Byte is split into the MAR what is happening (like where does the address from the MAR go to). What is the control matrix doing? Is it just choosing what to do with the MAR or what?. BTW your picture def. gave me a much better understanding of the RAM and how it's modeled. \$\endgroup\$ – user3073 May 23 '13 at 18:56
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    \$\begingroup\$ @Mercfh Sticking with that terminology and trying to keep it simple, the address in the MAR tells the address decoder which address lines to toggle. Once the RAM gets the address from the decoder, it puts the data at that address on the data bus where the processor can get at it. The opcode tells the control matrix what function to perform. So depending on the opcode, the control matrix will either move data from the data bus and put it in a register or it will move data from a register and feed it to the ALU or it will move data from a register back to RAM, etc. \$\endgroup\$ – embedded.kyle May 23 '13 at 19:11
  • \$\begingroup\$ So wait....does the PC go into the IR or MAR? Since your talking about the decoder going into RAM right? So it must be PC--->MAR--->Decoder--->RAM correct? Where is the IR in this setup? \$\endgroup\$ – user3073 May 24 '13 at 15:59
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    \$\begingroup\$ @Mercfh The PC goes into the MAR. When fetching an instruction, the address in RAM to get data from comes from the PC. When fetching data, the address comes from the address operand of the instruction. I've added a diagram that I hope helps. It includes a few more registers but if you ignore those the picture in your head should be a little clearer. \$\endgroup\$ – embedded.kyle May 24 '13 at 17:18
  • \$\begingroup\$ Wait you said the Address in RAM to get data comes from the PC?.....Ok im either really stupid or confused, Is the PC connected to the MAR and RAM or just the MAR. Diagram does help but I wish there was some sort of "line" drawn to show like the path it would take. (like even a MS paint line showing the path a simple instruction would do) \$\endgroup\$ – user3073 May 24 '13 at 18:14
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Since there are 16 bytes in the RAM you need 4 bits of address information to uniquely specify one of the RAM locations. Therefore, the MAR is 4 bits wide. The MAR doesn't store anything in RAM, it just provides an address. Even though the RAM has just 4 address lines it has 8 data lines, because each "address" in the RAM holds an entire byte. So, the MAR selects one of the 16 bytes in the RAM and the contents of that location appears on the data output bus from the RAM. It's this data that goes into the IR. There's no need for the 4 address bits to go into the IR since the processor already knows what value it stuck into the MAR. The 8 bits from the RAM, having been loaded into the IR, cause the processor to do something that may or may not cause something to happen in the accumulator.

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  • \$\begingroup\$ So the MAR is 4 bits wide, how does the instruction actually get into the MAR if it's only doing 1 bit at a time (like 0000 then 0001). If the MAR is 4 bits wide, it must have 4 different lines coming from the Counter into the MAR? I guess Im getting confused at whats happening from RAM---> IR. Since only the address (4 bits) is being stuck into the RAM (since thats all we have so far). what is coming out of the RAM (8 bits), where are the other 4 bits coming from (Since all we've gotten so far is the 4 bits/4 address lines. \$\endgroup\$ – user3073 May 22 '13 at 20:25
  • \$\begingroup\$ The instruction itself is never loaded in to the MAR. The MAR holds the address of an instruction. The 4 bits from the MAR aren't "going in" to the RAM, we assume that the RAM has been previously loaded with the desired instructions. It's important that you understand the difference between the RAM address and the RAM data. \$\endgroup\$ – Joe Hass May 22 '13 at 21:17
  • \$\begingroup\$ Ok so that poses another question, you said the address 4 bits aren't stored in RAM. So the MAR is using the address to look at where the RAM Data Instruction is, and then sending that out. Im assuming this RAM data is 8 bits? (4 bits opcode and 4 bits...something else?). From reading the Instructables the 4 bits opcode goes into Control matrix (makes sense) then the 4 bits address goes back into the MAR or program counter (Why would it go back in). I guess to summarize my question: What is coming out of the RAM. \$\endgroup\$ – user3073 May 22 '13 at 21:57
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    \$\begingroup\$ OK, I think I see why this is confusing. The contents of the RAM can be treated as instructions to be executed or as data to be manipulated. If the RAM location holds an instruction, then that instruction might need to get data from memory, and in that case the memory address for the data will be part of the instruction. The instructables is pretty vague about this. There must also be instructions that store data in the RAM and for those instructions there must be a path for data out of the processor and into the RAM. Sorry, this is a big topic. \$\endgroup\$ – Joe Hass May 22 '13 at 22:28
  • \$\begingroup\$ yeah it is a pretty big topic, but I think I understand what you mean. I think a small project for me to grasp is just getting data from counter ---> ram. Then ill work my way up through the rest. But I see what you mean when you say the RAM holds both, but yeah if data is going back in the ram...I see why you would need 8 bits of data bus going out of the ram. Since it might be data AND an opcode/instruction for instance. (or address/instruction i suppose). \$\endgroup\$ – user3073 May 22 '13 at 23:15

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