3 transistor XOR gate

Question

I am very new to electrical engineering.

But I am working on a hyper reduced fully functional RISC architecture. This is mostly finished, I have a compiler for it and the emulator is not fully complete yet but it seems to be fully functional, it is limited to 16 instructions with 1 of them reserved for extended instructions such as interrupt calls.

When working on silicon design (Not really on the silicon phase yet but circuit design) I noticed that the XOR gate seems overly complex.

Why would this not work:

^{simulate this circuit – Schematic created using CircuitLab}

I was was led to believe that the resistors were required for high frequencies to drain the circuit before next clock pulse.

I am new to this so if this is horribly wrong please correct me.

Answer 1

Why would this not work:

assuming series resistor should be a pull down this circuit will do XOR it will however do it better with the PNP transistor the other way round.

Also The output amplitude will be less than the input amplitude so some buffering is needed.

Other circuit designs use more parts to make them faster, stronger, or more energy-efficient.

Answer 2

There are a number of problems with this implementation.

What silicon process is this going on to? Implementing bipolar transistors resistors and diodes on a CMOS process is not area efficient you will probably find that this takes more silicon area than a conventional xor made from FETs. Below is a 10 transistor 'conventional' xor, note and1 and nor1 are a combined 6 transistor and-nor gate, your and gate alone is 6 transistors.

^{simulate this circuit – Schematic created using CircuitLab}

Although the design may do xor it has no gain. When you design a cell for a large design it is necessary to be able to characterize it for propagation delay and drive capability. This allows you to ensure that your design will meet its timing requirements with a reasonable amount of effort. The timing of your cell will be overly sensitive to the drive capability of the preceding cell and the type of load put on the output.

The cost per FET today is very low the big problem is power dissipation. This circuit will use far more power than a CMOS implementation.

Answer 3

I noticed that the XOR gate seems overly complex

At the most basic level, every gate implements a truth table. So, at a minimum, you could just have a programmable truth table, and you can get any gate you want. All you need then is a multiplexer:

^{simulate this circuit – Schematic created using CircuitLab}

As shown, the gate is configured to be an AND gate. The inputs 0-3 to the multiplexer are related to output values in the rows of a truth table. So, take the output column from a truth table, stick it into the circuit above, and you have a gate or any other logic function according to that truth table.

It is not particularly complicated to have a simple diode-transistor implementation of such a mux.

The 4-input multiplexer connects output to one of the inputs that are attached to either supply rail, so it always regenerates the signal.

With two inverters added, you can use a 2:1 mux instead:

^{simulate this circuit}

With a 4:1 mux, we had 4 inputs, and 2 choices of signals to feed to each input - VCC or GND (logic high or low). 2^4=16 possible gates.

With a 2:1 mux, we have 2 inputs, and 4 choices of signals to feed to each input: VCC, GND, IN1, not(IN1). 4^2=16 possible gates.

As shown, the configuration for both mux-gates is that of an AND gate.

Inverters are easy, and a 2:1 mux is not particularly hard either :)

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If I were you, I'd use off-the-shelf CD4000-series gates that you can buy from major vendors (DigiKey, Mouser, etc.), and also directly from TI (Texas Instruments), in either DIP or surface-mount packages. Every common chip in that family that has 14 or 16 pins is still available in DIP, brand new!

Below is the collection of the basic gates from the 4000 series, drawn myself. CD4049, CD4050, CD40109, CD4504 are level translators and you wouldn't need them. The processor made of these can be tuned for clock rate vs. supply voltage, just like desktop CPUs, and for the same reason. The higher the voltage, the faster it can go. CD4000-family can be slow and sip power at 3V, or rather zippy at 15V. With the chips of recent manufacture (last 15 years or so), peak speed is between 12V and 15V, with minimum gains from 12V up.

Not shown is the 8-input CD4048 configurable expandable gate that can be configured to be the gate of your choice :)

The reference for the entire CD4000 family that TI still makes, and a few interesting but obsolete parts in that family, in high-rez PDF and in Goodnotes format, are here:

CD4000 Logic Reference Cards.