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In VHDL, one can do this:

signal my_slv1       : STD_LOGIC_VECTOR(3 downto 0);
signal my_slv2 : STD_LOGIC_VECTOR(3 downto 0);

port map (
  [...]
  some_10bit_output(3 downto 0) => slv1,
  some_10bit_output(7 downto 4) => slv2,
  some_10bit_output(9 downto 8) => open
  [...]
);

Do Verilog and SystemVerilog permit this? The indication so far is that it is not permitted. I am specifically refering to the IEEE Std 1800-2009 standard of SystemVerilog.

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  • \$\begingroup\$ There is no port map in Verilog/SV. Can you show Verilog code for what you are trying to do? \$\endgroup\$
    – toolic
    Commented Feb 19 at 23:41
  • \$\begingroup\$ @toolic, I create instance of a module and then need to connect slice of it to a signal and leave other bits open similar to this VHDL example \$\endgroup\$
    – quantum231
    Commented Feb 20 at 0:33

1 Answer 1

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There is no direct corresponding feature in SystemVerilog. You cannot "break up" a single port connection into multiple connections. Trying to do this exactly the same way VHDL does may lead to frustrating results.

There are a number of different approaches you can take depending on whether it makes sense to modify the instantiated module declaration.

You can break up the module port declaration into several ports. It will be much easier to connect each individual port into a slice of another signals

my_module (output [1:0] o2bits, [3:0] slv2, slv1);
...
endmodule

You can join that signal inside the module if you want

my_module (output .o2bits(some_10bit_signal[9:8]), .slv2(some_10bit_signal[7:4]), .slv1(some_10bit_signal[3:0]));
  wire [9:0] some_10bit_signal; // internal signal name
  ...
endmodule

Then with either of these two declarations, you can instantiate it

my_module inst(.o2bits(), .slv1(my_slv1), .slv2(my_slv2) );

or my_module inst(.o2bits(), .slv1(some_8bit[7:4]), .slv2(some_8bit[3:0]) );

If you can't change the original module/entity port declarations, there are another set of approaches.

There is a concatenation expression:

my_module instance_name (.some_10bit_output({my_slv2,my_slv1}),... );

Note that Verilog right justifies the 8-bit concatenation with the 10-bit port, leaving the leftmost 2 bits of the port unconnected. If you want some other bits of the slice left unconnected, you can fill with a literal for input ports, or dummy wires for output port as part of the concatenation.

There is an aliasconstruct that maps pieces of a net to another net. This looks the closest to mimicking what you want from VHDL.

  wire [9:0] some_10bit_output;
  wire [3:0] slv1;
  wire [3:0] slv2;
  alias some_10bit_output[3:0] = slv1;
  alias some_10bit_output[7:4] = slv2;
  my_module inst (.some_10bit_output );

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  • \$\begingroup\$ ok, now here is the scenario, I have slv1 and the some_10bit_output, and these can't connect. What to do now? \$\endgroup\$
    – quantum231
    Commented Feb 20 at 0:34
  • 1
    \$\begingroup\$ I don't know what you mean by "these can't connect". The whole point of a port map is making connections between 2 entities. \$\endgroup\$
    – dave_59
    Commented Feb 20 at 1:38
  • \$\begingroup\$ ok, in my case, I tried to connect a port that is 4 bits, to a signal that is 1 bit. The compilation fails and says port width mismatch. This is implied by the "these can't connect" since compilation fails with error and is reason for this question. \$\endgroup\$
    – gyuunyuu
    Commented Feb 20 at 10:37
  • \$\begingroup\$ Is it a warning, or an error? It's certainly legal in SystemVerilog, but some synthesis tools do not allow it. If this is an output port, you might have to add dummy wires. It would help to show what you have tried in SystemVerilog. \$\endgroup\$
    – dave_59
    Commented Feb 20 at 15:44
  • \$\begingroup\$ I was getting error that basically said that port of width X is being connected to signal of width Y and there is signal mismatch. The compilation would not proceed. Anyway, what I have done since is to create a signal that has same width as the output of the module so the port width mismatch does not happen. Then, I take a slice of this signal to the actual final output. There seems to be no other way to make this worse as things stand. This one aspect of SystemVerilog does not seem to match VHDL. \$\endgroup\$
    – gyuunyuu
    Commented Feb 20 at 17:49

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