# Parameterized net width in Verilog

Is something like this possible ?

parameter width;
wire[width-1] a_net = (width)'b0;


I basically need a variable to control the width of the right hand side. I am planning to use this in an test bench where I just have to change the parameter width at the beginning of the file, and this parameter sets the net width in all other occurrences of 'a_net'.

If this doesn't work - is there any other workaround ?

You want to match the right hand side width with the declaration width to avoid tool warnings?

First use a 1-bit wide zero constant, this will be expanded using the Verilog expansion rules, which will give you an appropriate width zero:

wire [width-1:0] a_net = 1'b0;


If that generates a simulator/synthesiser warning your tools are outside of the Verilog spec. A common way to get around this is with the replication operator, which can take a constant width:

wire [width-1:0] a_net = {width{1'b0}};


You can do this with parameters is you want it just in one module:

parameter width = 8;
wire [width-1:0] a_net = 0;


For more than one module it's easier to do it with a define:

define WIDTH 8
wire [WIDTH-1:0] a_net = 0;