How to find syntax error in RTL file quickly?

Question

My company uses custom flow that is accessed via makefiles to compile the RTL and testbench code and run the simulation. The simulator cannot be accessed directly to open in GUI. The makefiles submit request to a central server. The RTL and testbench files are stored on server. The design is monstrous in size. If I run build for my portion that is 15% of the design, it will take 45 min. With optimization, it will still take 15 min.

My problem is that often the SystemVerilog RTL file I am working on will contain some syntax error like a missing semicolon or something else. The build process tells me about this once it has been running for 10 min or more. This means a LOT of wasted time. I am using Notepad++ editor.

The Notepad++ code is compiled and simulated using Xcelium. I cannot access the program directly but use the makefiles to submit a request to the server to compile the code.

Is there absolutely any way, any editor or otherwise, that will tell me if I have some stupid syntax error or a signal name that does not match what is declared or not found in the specified packages?

EDIT: The organization uses Spyglass for linting. However, again, it is not possible to access this tool directly. The only way is to access it via the custom flow i.e makefile. When the Spyglass is executed it takes around more than 10 min to complete linting of everything. In order to do its job, the linting tool first runs through part of the build process where automatic file generation is carried out. A lot of RTL files (e.g packages) are generated from simpler descriptions which makes the build process time consuming.

Is there a way perhaps to use VS Code or some other editor that will atleast find the stupid mistakes like semicolon and commas?

Answer 1

The first thing to do is report this extreme inefficiency up the chain of command at your company. It would be surprising if no one else has encountered this road-block. If you are lucky, they are aware and have a procedure already in place to mitigate this situation.

If not, they should explore the possibilities with Cadence to see if they can offer a different licensing model to allow more direct access to Xcelium or perhaps an incremental compile feature which would greatly reduce the compile time.

Other possibilities for you would be to use free software to read in some of your code. Icarus Verilog (iverilog) is free, but it has very limited SystemVerilog (SV) support. Verilator is also free, and it claims to fully support SV.

Answer 2

There was a tool for C called lint, this did what you are looking for but for C code.

A quick search has turned up a bunch of tools which do the same for System Verilog one them is named svlint it may be worthwhile taking a look at this.