I am working on a latching current limiter circuit and as part of it I'm using multiple LM139 comparators to implement a simple SR latch. This specific comparator has an open-drain output.

A latching current limiter is like a time-delayed load-switch. When an overcurrent event happens the high-side FET is first driven into linear region to limit the current into the load, and after a delay it is shut-off completely (latched) to protect it thermally. The LATCH output of the circuit pulls the gate of the high-side FET high.

I've adapted a bistable multivibrator circuit I found in this application note to achieve the SR latch functionality (CMP1).


simulate this circuit – Schematic created using CircuitLab

The latch is set by pulling high the SET node and reset by pulling high the RESET node which is driven by a diode OR (note that in the real circuit BAS40 diodes are used). The diode OR is driven by LM139 comparators, which implement the current sensing of the actual circuit.

The problem I have is that the initial condition of the latch is SET, and I would like to instead have it off at the beginning.

Adding a 100nF capacitor from LATCH to GND works, but induces a too high-current into the comparator when the latch is reset (~500mA) in simulation. I've then attempted to limit the current flow during reset by placing a series resistor between the capacitor and the LATCH node, but this again makes the latch be SET during startup.

How can I set the initial latch state?

I would appreciate general critique of this design before I implement it physically.


3 Answers 3


There is a way with the same comparators fewer resistors, and no diodes, but it will be a while before I can post a schematic.

To start, the comparators are open-collector so you can reverse their input connections and connect their outputs directly together, with no diodes, into a single pull-up resistor. This is effectively a diode-AND circuit, and changes the logic polarity at the "Reset" node. Start with that and work through the output.

UPDATE2 - Corrected Schematic:

First pass at an alternate approach. This is a concept schematic; it does not include power supply decoupling or treatment of the unused comparator.

enter image description here

Note that the A and B input polarity connections are swapped. This changes the logic polarity at the comparator outputs to work more favorably with open-collector outputs.

The input comparators drive the non-inverting input of the latch comparator, so the overall logic polarity from the + and - inputs to the LATCH output is preserved.

You don't say where your "Set" input signal comes from, so I indicate it with a switch. The switch pulls this comparator input low, while the Set input goes high in your schematic. This is the only functional change from the original circuit. If this is an issue, the 4th comparator section can be used to invert the Set input signal.

To solve your original problem, C1 is added to the design for power-on reset (POR). It holds the node you call "Reset" low briefly at power-up, forcing the LATCH output to a low state. If the POR function is not consistent, increase the value of C1.

Whenever one of the input comparators changes state, it shorts out C1. For some components this can be a problem, as the discharge current of a capacitor can be high enough to damage an output stage. However, the LM139 output stage is rated for a continuous short circuit to GND, and limits this current to 20 mA.

Follow-up questions:

R5 is the closest thing in my design library to your value of 1.3 K. Because of the extremely asymmetrical nature of an open-collector output stage, it does not figure into the circuit calculations.

R2-R3 set up a threshold voltage of Vcc/2, so the voltage at U1Cpin9 for the two stable latch states must be clearly above and below this.

When either U1a or U1b is low, they are very low. With a non-zero voltage at the latch inverting input, when the non-inverting input is pulled to GND, the output goes low no matter what the values of R1, R4, and R5 are.

When U1a or U1b releases, with the latch output staying low, there now is a voltage divider from Vcc to R1 to R4 to GND through the U1C output stage. For the latch to latch, the R1-R4 node voltage must be below the R2-R3 node voltage, so R1 must be greater than R4. Since there already are 10 K resistors in the circuit, making one of the divider resistors 10 K is a convenient starting point. After that, the question is how much hysteresis is enough. Since none of these resistor values are critical, I went with 22 K rather than 20 K as a more common value, for just over 2 V of hysteresis.

Alternatively, you could make R1, R4, and R2 equal, and increase R3 for the hysteresis voltage. But placing the reference at Vcc/2 makes things easier to guesstimate and visualize.

Note that the total hysteresis is asymmetrical as well. When the LATCH output is high and the circuit is resting, both sides of R1 are pulled to Vcc, and the resting voltage at the latch non-inverting input is 12 V. Thus, relative to the reference voltage, the total hysteresis is +6 V to -2 V. Even though the circuit has four operating conditions, there is only one design calculation. Gotta love me them open-collectors.

  • \$\begingroup\$ Thats super interesting! I've tried it as well, in the meantime, but both in my design and your example circuit the problem is that it does not stay latched. I'm expecting that when any of the input comparators goes into conducting mode (i.e. '0'), that the latch will follow it and then stays at '0', even if the input comparator again goes to high-Z. What I instead observe is that the latch comparator follows the input comparators at all times. Any ideas? \$\endgroup\$
    – Malte
    Commented Feb 21 at 15:43
  • \$\begingroup\$ Reverse R4 and R1. OOPS \$\endgroup\$
    – AnalogKid
    Commented Feb 21 at 15:49
  • \$\begingroup\$ Amazing, this works! I can't thank you enough. This is indeed much cleaner. \$\endgroup\$
    – Malte
    Commented Feb 21 at 15:56
  • \$\begingroup\$ If you don't mind, how did you come up with the pull-up and feedback resistor values (i.e. R1, R4, R5, specifically)? I'm trying to understand a bit how this is sized in general \$\endgroup\$
    – Malte
    Commented Feb 21 at 15:57
  • \$\begingroup\$ Start with R5. Make it "low" so that the output can be approximated to be push-pull relative to values of R1 and R4. Add R4, say 1/10 of the value output pull-up (R5), to provide latching action. Then size R1 so that it doesn't override the feedback, but provides extra charge current for C1. I imagine that this circuit would work without R1, but maybe I'm wrong about that. \$\endgroup\$ Commented Feb 22 at 16:55

You could add a third reset input driven by an RC circuit to give a power on reset, something similar to the marked up schematic below.

A general critique? I’d consider using a dual comparator and a digital latch/FF IC. If you used a chip with active low set/reset, you could eliminate the Schottky diodes as well.

POR mod


Connect this RC circuit to Reset. It affects the Latch after power-on only.

enter image description here


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