I am encountering issues with a LT8390 design, particularly in higher load current conditions, which leads me to suspect a stability problem. The design parameters are as follows: vin 18-36 (28v nominal), vout=20v, fsw=150kHz, maximum current=20A. I conducted simulations in LTspice and utilized .fra to generate a bode plot.
I understand that for stability, the design should have phase margin>60, frequency bandwidth<1/5 switching frequency. Examining the bode plot reinforces my suspicion of instability. The phase margin is almost zero!
Despite my awareness of the impact of output capacitors on pole and zero positions and the presence of a compensation circuit to address the output zero and pole, I am unable to achieve a phase margin close to 60 degrees, regardless of the capacitor values I select, with Rth=R9, Cth=c2, and RTp=C1.
I seek guidance on how to stabilize this circuit. Is there any rationale behind modifying the compensation (Vc circuitry) that could assist in achieving stability? I used the method explained here: Generate a Bode Plot for an SMPS in LTspice 17.1
I utilized LTPOWER CAD as recommended by @Voltage Spike, and now it appears that I am experiencing transient issues: