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enter image description here

I'm using the circuit above to control the common-mode voltage of the 2 resistors. M16 is a current source. The OpAmp controls common-mode voltage by adjusting the resistance of M20.

I need to adjust Vcm quite fast (I need a bandwidth of 5MHz) and the circuit tends to oscillate if I do so. So I tried to find the poles in the feedback loop and to place them properly. However, the only pole I could see is the one at the gate of M20 - \$ \frac{1}{2\pi R_{o} C_{gg}} \$ (but I didn't see this pole on the bode plot of the loop gain...) So where are the poles, and how can I compensate this circuit? (The GBW of the OpAmp is 1000M and DC gain is 100dB, Ro = 10 Ohm. Cgg of M20 is about 6fF)

I also attached the bode plot below, there are two poles according to the figure - one at 10kHz and another one at 10MHz.

enter image description here

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  • \$\begingroup\$ There is a low pass formed by drain source capacitance of M2 and R3. The required 5 MHz bandwidth with this large value of R3 is a problem. What is Cout of M20? \$\endgroup\$
    – Jens
    Feb 22 at 1:34
  • \$\begingroup\$ From the GBW of your op amp and the DC gain it has the first pole roughly corresponds to the 3dB (dominant pole) of the op amp and the second pole could be coming from the contribution of the op-amp internal nodes, input capacitance and drain capacitance of M16 \$\endgroup\$
    – snEE
    Feb 22 at 1:37
  • \$\begingroup\$ What's the nominal DC voltage of your V2 source? \$\endgroup\$
    – Designalog
    Feb 22 at 13:43
  • \$\begingroup\$ @Designalog It's 750mV, half of the VDD at the moment. \$\endgroup\$
    – George Guo
    Feb 22 at 15:50

1 Answer 1

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Look at the resistances and capacitances at each node and the op amp model. If what you've found can't explain your Bode plot, keep looking.

I would also not make assumptions about the Rout of either FET - they are described as '1v' NMOS/PMOS. I don't know what process you are using in your design, but the analog behavior of deep submicron FETs are very dependent on the particular optimization choices of a given process. I've worked on a 130nm process where L vs Rout was far different and non-ideal, compared to a 180nm and a 90nm processes I used for similar designs - the latter processes were far more 'friendly' for a traditional analog design such as this one.

Again, make no assumptions about any node.

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