This might be a out of stand question.I am trying to understand a verilog netlist for 1 bit adder and make schematic out of it.But as i am very new to Verilog, though can understand some basic commands.I had preferred reading this, but it didn't help me out.Below is the required netlist

module test(in1, in2, out);
input in1;
input in2;
output [1:0] out;

wire  synth_net;
wire  synth_net_0;
wire  synth_net_1;
wire  synth_net_2;

wire  synth_net_3;
wire  synth_net_4;
ADD2 synth_ADD(.in1({synth_net, in1}), .
    in2({synth_net_0, in2}), .cin(synth_net_1), .out({synth_net_3, synth_net_4})
    , .cout(synth_net_2));
GND synth_GND(.out(synth_net));
GND synth_GND_0(.out(
GND synth_GND_1(.out(synth_net_1));
BUF synth_BUF(.in(
    synth_net_3), .out(out[1]));
BUF synth_BUF_0(.in(synth_net_4), .out(out[0])

Well variable declaration is understandable.But i can't understand

ADD2 synth_ADD(.in1({synth_net, in1}), .
        in2({synth_net_0, in2}), .cin(synth_net_1), .out({synth_net_3, synth_net_4})

1 Answer 1


Your netlist has created tie cells, effectively a good electrical 0 or 1.

The have been created using GND cells and they drive your wires similar to synth_net.

{a,b} is a concatenation operator if a & b are 1 bit each you will have a 2-bit value which looks like ab.

Therefore {synth_net, in1} is effectively in1 with a 0 (GND) added to the MSB.

The Article you linked to only seemed to show ordered port list connections, I prefer to use named connection as you have in your netlist.

ADD2 synth_ADD(
  .in1( {synth_net, in1}  ), 
  .in2( {synth_net_0, in2}),
  .cin( synth_net_1       ),
  .out( {synth_net_3, synth_net_4})

The above is an instance of ADD2 this instance is called synth_ADD. synth_ADD has ports in1, in2, cin and out. Looking at the instantiation we can see that in1 is being driven by {synth_net, in1}.

  • \$\begingroup\$ :ok that is well taken.One more thing, when we manually draw this schematic, all other ports are utilized along with all wire but where in schematic we will use BUF and GND \$\endgroup\$
    – shailendra
    May 23, 2013 at 11:22
  • \$\begingroup\$ Not sure I follow exactly, if schematic is just representation then connection to Supply or ground could be used. BUF, a buffer normally added of the correct drive strength for illustration purposes could be missed but you will require it in larger systems to make sure your design meets your timing constraints. A high drive strength buffer will not be slewed as much over long tracks. BUF and GND should come from your base libraries, you should have schematics for these. \$\endgroup\$ May 23, 2013 at 11:34
  • \$\begingroup\$ now i am able to validate the output of synthesizer which was converting a verilog file to verilog netlist which i had used above.They both seems to validate each other , so my test case is successful.This link help me to understand further. \$\endgroup\$
    – shailendra
    May 23, 2013 at 15:03

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