Understanding Verilog Netlist

Question

This might be a out of stand question.I am trying to understand a verilog netlist for 1 bit adder and make schematic out of it.But as i am very new to Verilog, though can understand some basic commands.I had preferred reading this, but it didn't help me out.Below is the required netlist

module test(in1, in2, out);
input in1;
input in2;
output [1:0] out;

wire  synth_net;
wire  synth_net_0;
wire  synth_net_1;
wire  synth_net_2;

wire  synth_net_3;
wire  synth_net_4;
ADD2 synth_ADD(.in1({synth_net, in1}), .
    in2({synth_net_0, in2}), .cin(synth_net_1), .out({synth_net_3, synth_net_4})
    , .cout(synth_net_2));
GND synth_GND(.out(synth_net));
GND synth_GND_0(.out(
    synth_net_0));
GND synth_GND_1(.out(synth_net_1));
BUF synth_BUF(.in(
    synth_net_3), .out(out[1]));
BUF synth_BUF_0(.in(synth_net_4), .out(out[0])
    );
endmodule

Well variable declaration is understandable.But i can't understand

ADD2 synth_ADD(.in1({synth_net, in1}), .
        in2({synth_net_0, in2}), .cin(synth_net_1), .out({synth_net_3, synth_net_4})

Answer 1

Your netlist has created tie cells, effectively a good electrical 0 or 1.

The have been created using GND cells and they drive your wires similar to synth_net.

{a,b} is a concatenation operator if a & b are 1 bit each you will have a 2-bit value which looks like ab.

Therefore {synth_net, in1} is effectively in1 with a 0 (GND) added to the MSB.

The Article you linked to only seemed to show ordered port list connections, I prefer to use named connection as you have in your netlist.

ADD2 synth_ADD(
  .in1( {synth_net, in1}  ), 
  .in2( {synth_net_0, in2}),
  .cin( synth_net_1       ),
  .out( {synth_net_3, synth_net_4})
);

The above is an instance of ADD2 this instance is called synth_ADD. synth_ADD has ports in1, in2, cin and out. Looking at the instantiation we can see that in1 is being driven by {synth_net, in1}.