I'm trying to make a one-time, "turn-on-once" switch. I've made a simpler design before, but I seem to have lost it. 

So basically, when the comparator is pulled to high, the switch turns on indefinitely, or at least until the system power turns off.

So here's what I got thus far:

enter image description here

When I press the push button and if the clock is on, then the switch turns on indefinitely as shown below (LED turns on "forever"):

enter image description here


  1. The problem is that this is clock dependent, so it might not be reliable. Perhaps I should use a circuit that's not clocked?

  2. Is there a way to do this without using the OR gate? Is there a simpler design?

  • 2
    \$\begingroup\$ I guess I don't follow. I'm probably not thinking well. Why not tie the switch to the clock input of the FF and tie the D input to "1"? \$\endgroup\$ Feb 22 at 11:47
  • \$\begingroup\$ And wire the LED with the resistor to \Q and +5V. \$\endgroup\$
    – Antonio51
    Feb 22 at 11:50
  • 2
    \$\begingroup\$ This is far too complicated for what you are trying to achieve and probably will not work. What is the state of the flip flop on power up? \$\endgroup\$
    – RoyC
    Feb 22 at 12:34
  • 3
    \$\begingroup\$ You really just need an R-S latch, created from a pair of cross-coupled NAND or NOR gates. \$\endgroup\$
    – Dave Tweed
    Feb 22 at 16:16
  • \$\begingroup\$ Or any Schmitt Trigger circuit will do, where the hysteresis is so, that pressing the button will trigger it, but releasing it, will keep it going (e. g. reset point is a negative voltage). So a Schmitt Trigger or an R-S latch will give you a nice clean rising edge - without any bounce effect like the @David Tweeds solution would have - it depends on what your output serves for. \$\endgroup\$ Feb 23 at 22:09

6 Answers 6


The simplest circuit is probably a relay


simulate this circuit – Schematic created using CircuitLab

Could be mechanical or solid-state; works either way.

  • \$\begingroup\$ This is very simple solution. If you do not care about bounce effect of SW1 until the switch of RLY closes/bounces too, then it is a valid solution. \$\endgroup\$ Feb 23 at 22:12
  • \$\begingroup\$ Thanks Dave. My idea is simply to detect a zero-cross. Once it's detected then to turn on a 555 timer. Here is a more detailed layout: electronics.stackexchange.com/questions/703794/… \$\endgroup\$ Feb 25 at 13:02
  • \$\begingroup\$ The idea is to sync the 555 with the out AC waveform \$\endgroup\$ Feb 25 at 13:03

You can make latch from two mosfets.

PB triggers the latch and stays On (Out High) until SW is released.

10uF capacitor initialises the latch to Out Low.

Bat46 accros 47k serves for quick discharge of 10u after SW is Off to be ready for next Power-On.

enter image description here

Simpler solution is to use just one low power SCR thyristor and trigger its gate with push-button.

Edit: If you plan to trigger it with Push-button only (low speed) you can avoid the initialising circuit just placing the 100n cap to gate:

enter image description here


I'd ditch the comparator and latch and just use a single or gate with 2 resistors like this:

enter image description here

At startup,the resistors make sure that the output of the OR gate is initialized to 0. Once it sees the high signal once, it latches itself high. (Might want a resistor before the LED; I forgot about that). Try simulating it in Falstad here!

Resistor values in the range ~5k - 100k will be good. Resistors on the lower end of this range are better if you're not power constrained.

This solution is similar in spirit to Dave Tweed's relay answer, but I think an or gate makes a lot more sense than a relay. A relay (even a solid state one) is absolutely overkill for this application; a discrete or gate is ~5x cheaper than the cheapest solid state relay on Digikey. An or gate IC will also be smaller.

Some other more exotic answers might be better in terms of absolute transistor count, but assuming you're designing a PCB, a single OR-gate IC is better than 2 separately packaged MOSFETS. If this is for a class or something where they're asking you to design with the fewest number of transistors possible, some of the other, more creative answers will be better.

  • \$\begingroup\$ Other than the missing LED resistor - n.i.c.e. \$\endgroup\$
    – AnalogKid
    Feb 23 at 22:47
  • \$\begingroup\$ I like this solution but it does have the (unlikely and somewhat contrived) error case where if the gate's output glitches high during power up it could reach around and latch itself on. \$\endgroup\$
    – td127
    Feb 23 at 23:20
  • \$\begingroup\$ I don;t think it could turn high at power up with both inputs tied to GND with pull down resistors. Reduce the value of the pull down resistors if necessary. I didn't try it, but theoricaly it should work. \$\endgroup\$
    – Fredled
    Feb 24 at 0:14
  • \$\begingroup\$ @td127 yeah, that's why I added the pulldown resistors. Thinking through the internals of the or gate, I think it would take a freak accident to make that happen. \$\endgroup\$
    – John M
    Feb 24 at 0:34
  • 1
    \$\begingroup\$ Hey john. Thanks for the feedback. This is where I basically wish to apply this idea. electronics.stackexchange.com/questions/703794/… I want the 555 timer to switch on as soon as a zero cross is detected. this will synchronize it with the AC curcuit signal allow me to clip the AC waveform and hence dim the lights. \$\endgroup\$ Feb 25 at 13:08

I have a couple ideas to make a latch. The first 3 circuits use parts you left me to work with. The additional circuits are just ideas I had while drafting this. There's at least 12 other ways this could be done. But this should be a good start:


simulate this circuit – Schematic created using CircuitLab

In circuit 1, the rectifier may be omitted if you are using open-collector comparators. You can possibly eliminate the resistor that follows it.

Circuit 2 digital feedback to maintain the latch. The capacitor guarantees proper logic levels at power up.

Circuit 3 works similar to Circuit 2. No clock signal necessary. You could use the clock input, but the circuit would be different.

Circuit 4 is a typical NAND latch with ensured start up logic (same idea as circuits 1, 2 & 3).


simulate this circuit

Circuit 5 another logic latch using NOR technology.

Circuit 6 another logic latch using inverters.

Circuit 7 transistor based latch works similar to SCR functionality.

Circuit 8 opto-isolator based design.


First, realize that your proposed circuit has a flaw: what is the power-on state of the D flip-flop? It needs a reset. It's even worse that they're unconnected CMOS inputs, which is a definite no-no.

Your circuit could be simplified as follows, just by using that flop alone (simulate it here):

enter image description here

The R-C connected to the R (reset) pin generates a positive pulse at power-on to set the flop in the right initial condition. Notice also that I have connected the S (set) pin, to GND. This is required.

Even if the switch bounces, we don't care - the flop will get clocked regardless.

Another method: a Schmitt-trigger type circuit can do this. A couple of ideas below (simulate them here)

enter image description here

Both work on the same principle: positive feedback to the input, and again an R-C delay to ensure the correct power-on state. You'd use this in place of the flop.

You could also construct a Schmitt trigger from your op-amp, but that seems wholly unnecessary.


According to the Function Table, you just have to keep D high all the time, and at the first clock pulse, Q will turn high. The following clock pulse will keep Q high too, so no change will happen.

If Q is on by default when power is on, just keep D low and use -Q instead.

Connect CLK directly (see Note) to the tact switch. One clock pulse and here you go.

(Note: Add a 10K resistor between the switch and CLK to protect it. See also debouncer circuits and components.)


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