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To consider the effect of loading in a shunt-shunt amplifier that is being analyzed with two port analysis, we short the feedback network at the input/output to calculate loading at the amplifier output/input.

Also, inverting amplifier topologies are often analyzed as shunt-shunt configurations after a Norton transformation is applied at the input.

Consider the following switched-capacitor (SC) integrator below. The input is sampled onto C1 during one clock phase (even-numbered switches closed) and integrated onto the feedback capacitor during the second clock phase (odd-numbered switches closed).

How would I model the open loop amplifier with feedback network loading during the sampling phase? If SW2 is closed, and I short the feedback network at the amplifier input to consider loading at the amplifier output, then the amplifier output is shorted. This would predict 0 loop gain for the circuit in the sampling phase, which I do not think is true.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ From my POV the output can never be shorted as long as \$C_1\$ isn't shorted. Do I understand correctly that always either the odd or the even switches are closed? I don't understand what you mean by: "If SW2 is closed, and I short the feedback network at the amplifier input to consider loading at the amplifier output, then the amplifier output is shorted." \$\endgroup\$
    – HarryH
    Commented Feb 26 at 22:34
  • \$\begingroup\$ @HarryH in two-port feedback analysis, you decompose the circuit into an ideal feedback network and forward amplifier with loading due to the real feedback network. In the shunt-shunt topology, the feedback network is shorted at the amplifier inputs to calculate loading at the amplifier output. \$\endgroup\$
    – DavidG25
    Commented Feb 26 at 23:53
  • \$\begingroup\$ Ok, got you, sorry for being slow. With SW2 closed there is no real feedback, or only some degenerated kind of it, fixing the right side of C1 to ground, requiring a different approach. With SW2 closed and OA1 considered 'ideal', there is no feedback but rather C1 effectively connected to ground and C2 disconnected with the right side connected to ground. Only with SW2 open there's an amplifier with a feedback. Hope this is not too much nonsense... \$\endgroup\$
    – HarryH
    Commented Feb 27 at 3:45
  • \$\begingroup\$ @HarryH I think you are saying that this is not a feedback circuit during the sampling phase (i.e. SW2 closed) and feedback analysis doesn't apply. I'm not sure: the only reason you can say C1 is connected to ground is because of feedback. Physically, it's only connected to the input and output of an amplifier, not ground. Those nodes are high impedance without feedback (in the typical case of an OTA for the amplifier). \$\endgroup\$
    – DavidG25
    Commented Feb 27 at 16:29
  • \$\begingroup\$ It may be confusing because we typically think of the loop gain as being sufficient/insufficient based on the input-output behvaior of a circuit. Here, the primary metric is the input impedance, but that is also a function of the loop gain. \$\endgroup\$
    – DavidG25
    Commented Feb 27 at 17:21

1 Answer 1

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The amplifier output is not shorted; it can be modeled as a unity-gain amplifier with an input of zero volts driving capacitor C1. Assume C2 starts at zero volts, and Vin is a constant. C1 is charged to VIN:

enter image description here

When SW4 opens and SW3 closes, the right side of C1 is instantaneously at -VIN. But SW2 opens and SW1 closes and OA1-output is driven positive to until OA1-minus input is back to zero. This occurs when its output voltage is C1/C2:

enter image description here

At the next interval, C1 is once again charged to VIN, but C2 retains its charge:

enter image description here

As before, when SW4 opens and SW3 closes, the right side of C1 is instantaneously at -VIN. But this time when SW2 opens and SW1 closes OA1-output must drive more positive to get OA1-minus input back to zero, because C2 already has a voltage of -C1/C2. Therefore, OA1 output must reach 2(C1/C2):

enter image description here

So what you have is a variable integrator, whose time constant can be adjusted by varying the frequency of the switches.

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  • \$\begingroup\$ The question is about the feedback analysis of the circuit in the sampling phase, not the operation of the circuit. You are suggesting that the circuit is no longer a shunt-shunt topology in the sampling phase but rather a series-shunt. That answers the question. Please post something on my other bountied question so I can award both bounties to you. \$\endgroup\$
    – DavidG25
    Commented Feb 29 at 21:39
  • \$\begingroup\$ Consider editing your answer to focus on the fact that it is a series-shunt circuit in the sampling phase and therefore the calculation for feedback network loading is different. \$\endgroup\$
    – DavidG25
    Commented Feb 29 at 21:40

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