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I am planning to use MSP430F6638 for SPI Communication between a single MSP430 Master and multiple MSP430 Slaves. I am using a 4x16 Multiplexer before each Slave for providing the Chip Select Signal. This allows for using 4 GPIO wires to address 16 Slaves. I am curious about the following issues and would like to have suggestions about the possible solutions.

  1. The wire distance goes up to a maximum of 10m, will I face clock synchronization issues? What can I do to solve it?
  2. Should I use unidirectional line buffers on the CLK, SOMI, MOSI pins and Chip Select GPIO wires in order to be able to address 16 Slaves? As for the fan-out, the MSP430 datasheet says (as I understood) that fan-out must not increase 48mA on all pins combined and I am using some other peripherals simultaneously, so it’s difficult to calculate the remaining capability.
  3. Should I try going for a Daisy-Chain configuration? Does anybody have experience of writing software for Daisy Chain? Will it be of help using a Real Time Operating System or SYS/BIOS for writing the complex firmware required in case of Daisy Chain?

I would highly appreciate useful suggestions and comments. Thanks

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    \$\begingroup\$ What clock speed are you planning to operate at? \$\endgroup\$
    – Andy aka
    May 23, 2013 at 17:36
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    \$\begingroup\$ The SPI pins aren't really designed with 10m wire in mind. You probably need/want a driver that is able to drive the cable capacitance and protects the chip from noise/spikes/ESD/... You also may need some sort of pulse shaper for the receiving end, which also should protect the circuit. \$\endgroup\$
    – jippie
    May 23, 2013 at 19:10
  • \$\begingroup\$ In electronics, especially where low voltages and currents are involved (on MISO, MOSI lines) keeping the wires short is a good way of implementation. As far as CLK is concerned, long wires will cause an increase in resistance (although negligible) but this causes the clock to sometimes miss a beat or improper clock signals which may cause square waves to be like triangular waves. The reason I have explained this is because I have made exactly the same mistake before and had A LOT of problems \$\endgroup\$ May 24, 2013 at 1:44
  • \$\begingroup\$ Also, a brief schematic displaying all components and connections would be great to help you answer your question \$\endgroup\$ May 24, 2013 at 1:47
  • \$\begingroup\$ @Andy aka Currently I have performed communication with 2 Slaves and 1 Master using the 4MHz Clock source, but I can go for a lower range as well if required. \$\endgroup\$
    – Hammad
    May 24, 2013 at 10:55

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(Hopefully) Useful suggestions and comments: -

Your clock speed is not unreasonable but you have to maintain shape so some care in using line drivers and receivers is needed. Another thing you have to watch out for is that when you poll a slave, it will respond synchronized with the clock it receives and drivers and cable introduce delay.

No problem at the slave end but when the reply is sent from the slave, the total delay up and down the line may, on fast clocks push the received symbol too much out of skew with the clock the master is using to "collect" the data. Something to watch out for.

Regarding your 4:16 line CE idea - the slaves are intelligent, why don't you embed an address into each slave and the master transmission then, only the correct slave will respond. It's a little more overhead but I get the impression is isn't a critically fast application. This of course is taking you down a kind of synchronized RS485 scheme which leads me to ask why this isn't considered for your application; running unsynchronized will not cause clock skew errors and at your data rate, 10 metres is easy.

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  • \$\begingroup\$ Thanks @Andy aka, as far as I know, SPI don't allows communication with more than one slave at a time. The Transmit and Receive operations are carried out simultaneously i.e. full duplex. Any Slave receiving data is transmitting as well using the same clock. The only way for SPI is either polling individual slaves or arranging them in a daisy chain configuration. \$\endgroup\$
    – Hammad
    May 28, 2013 at 14:00

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