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I want to know what is the use of default initialization in SystemVerilog.

How are

int a[3] = '{3{2}}; 

and

int a[3] = '{default: 2} 

different? Won't repetitive initialization serve the same purpose as default initialization?

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2 Answers 2

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There are many features in SystemVerilog that overlap with one another. In simple cases they may seem redundant, but as you expand into more complex scenarios, the value of one over the other becomes more clear. Take a 2-dimensional array

int a[2][3]='{2{'{3{0}}}};

Not only do you have to remember the number of elements to replicate, but also the shape of the array. Keeping all those {} in balance becomes a chore.

int a[2][3]='{default:0};

The default is much easier to understand. It's also useful when you net to set specific values for only some of the elements

int a[100] = '{0:1, 99:-1, default:0};

The default has a special behavior for associative array by setting element values without allocating space for them.

int a[bit[31:0]] = '{0:100, 1:200, default:-1}; // only two elements allocated
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Your 2 declarations result in the same initialization. This can easily be proven by running a Verilog simulation with the self-contained code below:

module tb;

initial begin
    int a[3] = '{3{2}};
    $display("no default  : %p", a);
end

initial begin
    int a[3] = '{default: 2};
    $display("with default: %p", a);
end

endmodule

Output:

no default  : '{2, 2, 2} 
with default: '{2, 2, 2} 

Refer to IEEE Std 1800-2017,section 10.9.1 Array assignment patterns:

It can sometimes be useful to set array elements to a value without having to keep track of how many members there are. This can be done with the default keyword:

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