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I am working on a project that requires the usage of a AD7656 16-bit high speed converter. This chip comes in a 64-LQFP package, which means the package is rather small. Because the prototype boards will be hand soldered, I'm using 100nF 0603 X7R decoupling capacitors in combination with 10uF 1210 ceramic, as a minimum recommended amount in the datasheet. I can't use smaller capacitors, furthermore the footprints are set on Medium density to make it possible to hand solder them.

Unfortunately there isn't a recommended layout specification of this IC available. I have problems routing the decoupling caps. It's impossible to place both the 100nF and 10uF together closely to the IC, whilst maintaining space for the signals (parallel bus, etc.) to get out as well.

Now I have got 2 choices:

  • I place the decoupling caps to the back of the PCB, which I don't use around the A/D and MCU for noise purposes.

  • I place the caps further away, but that might get to a distance of 5 cm.

Placing the caps to the back of the PCB seems like the easiest solution, maybe with paralleling 2 via's to the top to reduce the loss of the PCB. My question is, will this 'work' i.e. how will this affect the performance and noise? Or would I be better of keeping all of the capacitors at the top of the PCB?

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    \$\begingroup\$ The analog is coming in differential, or is it single ended? When you get to higher precision like 16bit it is near impossible to pull it off without a differential signal coming in. \$\endgroup\$ – Kortuk Nov 21 '10 at 15:33
  • \$\begingroup\$ The signal is single ended. The source is a differential signal with relative high common mode voltage (about 12V) and very weak (gain up to 5000x with very low noise pre-amps). Yes I know the A/D converter has a SNR of 'only' 84dB which is more like 14 bits. \$\endgroup\$ – Hans Nov 21 '10 at 16:43
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I almost always place the decoupling caps immediately under the device for which they are decoupling (though if you can fit the 100 nf on the top side, that's fine).

Generally, you want 1 via per power pin, and you want to place the via as close to the pin as possible, and the 100 nF cap as close to the vias as possible. Also, make the vias as large as will fit. This devices does not have a exposed pad on the bottom, which makes things easier.

The bottom layer is then used for power routing, and the top is for signals.

Putting the decoupling components directly under the part is generally only a problem when you are doing manufacturing, because boards with all components on the top are cheaper than boards with components on both sides.

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  • \$\begingroup\$ For now it is only a prototype and will not be manufactured in high numbers (less than 5). The device has a lot of people lines though, atleast 10 analog that need proper grounding. \$\endgroup\$ – Hans Nov 21 '10 at 14:48
  • \$\begingroup\$ I agree. You want to keep a good solid ground plane on bottom, but put the decoupling directly under the chip, if you can get the 100nF on top that would be better, as it is to decouple RF noise and the VIAs will add a bit of inductance and make that job hard. \$\endgroup\$ – Kortuk Nov 21 '10 at 15:32
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    \$\begingroup\$ to add to what kortuk said, in a production design you'd probably want 10nF caps as well, anything under 100nF really needs to be on the surface, the inductance of the via would completely nullify its capacitance at the frequencies its there to decouple. \$\endgroup\$ – Mark Nov 21 '10 at 18:23
  • \$\begingroup\$ @Mark, Spot on, I stopped as my comment already seemed long enough. As a side note for others, research has been done to show that most of the time (more than 90%) that people think they have signal integrity issues they actually have power integrity. This study was done of those already following professional practices, I am sure laymen such as ourselves will have signal integrity problems also, but just an interesting sidenote. \$\endgroup\$ – Kortuk Nov 21 '10 at 19:19
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    \$\begingroup\$ @kortuk I believe it, its not taught much. The first time i did a full power supply ripple/coupling analysis was just the after the first time i had a product fail FCC. \$\endgroup\$ – Mark Nov 21 '10 at 19:23

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