Choosing an adequate op-amp for shunt resistor sensing in SMPS applications

Question

I would like to get some industry experts / design engineers opinion about potential methods to improve the proposed shunt resistor current sensing method below. The intention is to improve this circuit from op-amp stability point of view while using best practices to apply a correct filtering method.

• When Q8 MOSFET is ON, the source (V_CS) voltage is attenuated by half. This method is used to improve SNR at low current levels.
• I am using 220 nF "lag capacitor" between op-amp inputs to improve/slow down the step voltage when current is flowing through the shunt resistor. There is no filtering applied after an op-amp.
• The closed loop gain = 10. The reference voltage is 1/2 of VDD = 1.65V using a simple voltage divider (R17||R18). The maximum voltage across the capacitor is up to 300 mV. However, with "GAIN_CTRL" enabled that voltage will be 150 mV.
• In the initial design OPA358 was used that has relatively fast slew rate (55 V/µs) and an GBW = 80 MHz.
• The narrowest pulse during which current flows through R_CS is around 580 ns. The sample is acquired in the middle with sampling time of 125 ns.

Requested additional information:

Low side current sense resistor is placed on a separate power board. [L1 - RED, L2 - ORANGE]

The differential CSR signal goes through a gold plated 2 mm connector that connects to the op-amp circuit input shown below. Note, there is a ground pour on L2 (not shown in this image). [L1 - RED, L4 - GREEN]. Copper pour in GREEN is +3V3.

QUESTIONS

1. Are there better solutions to filter out noise in this particular op-amp configuration as opposed to placing 220 nF (C22) cap between op-amp inputs? There is some additional information that I found about this method:

This capacitor is called a “lag capacitor.” The technique can be applied to amplifiers that have poor step response (excessive ringing) or circuits that are exposed to harsh EMI environments. Lag capacitors should be used with caution.

2. What is the minimum GBW of the op-amp that would satisfy this application? Provided that A_cl = 10 and the current ripple is (66.6 kHz * 2) = 133 kHz, op-amp with 2 - 3 MHz should be sufficient, correct? I do understand that a certain overhead is required when considering G * BW product, but OPA358 with 80 MHz seems like an overkill for this now.
3. Would reducing resistor values by maintaining the same ratio, improve the op-amp functionality (responsiveness, noise, stability)? I am aware that it comes at a cost in terms of higher current consumption.
4. I am considering to replace OPA358 with OPA607 instead. It comes with lower GBW of 50 MHz and lower slew rate of 24V/us (still sufficient), but with lower offset and better noise figures. However, I am not sure about the stability. If instead, someone knows an alternative device that could satisfy/improve this application I would really appreciate it. I shall add that the cost is of certain importance too.

UPDATE

I captured the output of the OPA358 and this is what I am presented with. Too much parasitic inductance potentially? This is not even the worst case scenario, but you can clearly see that if the pulse was even shorter, a big undershoot of this pulse would make it into the sampling window leading to a wrong inductor current measurement. There is a bit of jitter present in the image due to duty ratio adjustment. The sampling window is denoted by START and FINISH markers.

Answer 1

There's not much to the circuit from the op-amp stability POV, other than it being a bit overcomplicated for what it does. You have a ground-referenced current sense resistor. There's no need for a poor-man's differential amplifier setup. That kills the CMRR unless the resistors are matched as well as the op-amp's CMRR ability dictates. In other words: the circuit only works on paper if you assume the resistors are ideal.

The 10k/100k gain resistors are about an order of magnitude too high for a fast step response application. 1k/10k would be in the right ballpark. I'd start with something like this:

^{simulate this circuit – Schematic created using CircuitLab}

The circuit feeds a differential ADC input, well-poised to resolve fast common-mode swings.

R1 models the parasitic resistance between the ground plane and the bottom of the sense resistor.

Are there better solutions to filter out noise

What noise? The amplifier has a low gain and won't contribute appreciable noise relative to the ADC. You can always lower the amplifier's bandwidth, but eventually it'll be slow enough that the accuracy of the sampled pulse will suffer, as the output won't have enough time to settle. A capacitor in the feedback path of the op-amp will do that job just fine. No need for a capacitor across the sense resistor.

To capture the pulse amplitude with reasonable fidelity you'll need at least 1MHz of closed-loop bandwidth. That means at least a 20MHz GBW op-amp, with a safety factor of 2. Given that it'll have to drive the capacitive inputs of an ADC, a faster op-amp will do a better job. Go for 20-50MHz GBW, and evaluate the settling with the actual ADC load you'll be using.

It'd be preferable to have an ADC that can take several samples of the pulse, instead of just one - especially if this is used for closed-loop control rather than off-line data acquisition. You need to implement some feasibility checks on the data, and having more than one sample within the pulse will contribute towards that goal. A Kalman filter based on a model of the system that generates those pulses will further aid in cleaning up the data.