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I am seeing a strange behaviour on an I2C waveform, and it is causing an incorrect bit to be read by the master. The master device is an ET1200 EtherCAT ASIC, and my slave is a CY8C3666LTI PSoC which is emulating a 16-bit address EEPROM.

I2C Circuit

The master is attempting to read a few bytes from the 'EEPROM'. On the logic analyser and oscilloscope, the waveform looks like this:

I2C Waveform with bas clock pulse

The logic analyser is interpreting the waveform correctly. The bytes 0x24, 0x04, 0x30, 0x05, etc. can be seen written along the top. However, the ET1200 is seeing every other byte have the top bit set. So it's seeing 0x24, 0x84, 0x30, 0x85, etc.

Looking closely at those bits on the oscilloscope, we can see a malformed clock pulse there. And it's also so close to the preceding data bit, that it's not surprising that a 1 is being seen.

My question is: What could be causing this malformed clock pulse? Has anyone seen this before?

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  • \$\begingroup\$ Is the slave part doing clock stretching? And is this implemented in hardware or software? \$\endgroup\$
    – The Photon
    May 24, 2013 at 15:50
  • \$\begingroup\$ @ThePhoton - Good question. I'm pretty sure it's not. According to the datasheet, clock stretching only happens when the device is exiting sleep mode. I'm not entering sleep mode, so it shouldn't be happening. Also, the false positive is happening multiple times during the read. \$\endgroup\$ May 24, 2013 at 16:08

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"What could be causing this malformed clock pulse? Has anyone seen this before?"

When I've seen this problem it's been because I didn't code my I2C driver correctly. It's usually something along the lines of incorrectly setting the I/O pin to an input for a few clock cycles while nothing else on the I2C bus is driving it. This causes the pullup resistor to start to drive the line high before the somebody reasserts the data line.

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