How much does it cost to have a custom ASIC made?

I have browsed several ASIC manufacturer's webs, but I haven't found an actual number. I assume there would be a fixed cost associated with creating masks and such and then there will be a cost per unit.

Note: that I don't actually want to have an ASIC made, I'm just curious.

I looked into ASIC's a while ago and here's what I found:

Everybody has different definitions for the word "ASIC". There are (very roughly) three categories: FPGA Conversions, "normal" ASIC, and "full custom". As expected, these are in order of increasing price and increasing performance.

Before describing what these are, let me tell you how a chip is made... A chip has anywhere from 4 to 12+ "layers". The bottom 3 or 4 layers contains the transistors and some basic interconnectivity. The upper layers are almost entirely used to connect things together. "Masks" are kind-of like the transparencies used in the photo-etching of a PCB, but there is one mask per IC layer.

When it comes to making an ASIC, the cost of the masks is HUGE. It is not uncommon at all for a set of masks (8 layers, 35 to 50 nm) to run US$1 Million! So it is no great surprise to know that most of the "cheaper" ASIC suppliers try very hard to keep the costs of the masks down. FPGA Conversions: There are companies that specialize in FPGA to ASIC conversions. What they do is have a somewhat standard or fixed "base" which is then customized. Essentially the first 4 or 5 layers of their chip is the same for all of their customers. It contains some logic that is similar to common FPGA's. Your "customized" version will have some additional layers on top of it for routing. Essentially you're using their logic, but connecting it up in a way that works for you. Performance of these chips is maybe 30% faster than the FPGA you started with. Back in "the day", this would also be called a "sea of gates" or "gate array" chip. Pros: Low NRE (US$35k is about the lowest). Low minimum quantities (10k units/year).

Cons: High per-chip costs-- maybe 50% the cost of an FPGA. Low performance, relative to the other solutions.

"Normal" ASIC: In this solution, you are designing things down to the gate level. You take your VHDL/Verilog and compile it. The design for the individual gates are taken from a library of gates & devices that has been approved by the chip manufacturer (so they know it works with their process). You pay for all the masks, etc.

Pros: This is what most of the chips in the world are. Performance can be very good. Per-chip costs is low.

Cons: NRE for this starts at US$0.5 million and quickly goes up from there. Design verification is super important, since a simple screw-up will cost a lot of money. NRE+Minimum order qty is usually around US$1 million.

Full Custom: This is similar to a Normal ASIC, except that you have the flexibility to design down to the transistor level (or below). If you need to do analog design, super low power, super high performance, or anything that can't be done in a Normal ASIC, then this is the thing for you.

Pros: This requires a very specialized set of talents to do properly. Performance is great.

Cons: Same con's as Normal ASIC, only more so. Odds of screwing something up is much higher.

How you go about this really depends on how much of the work you want to take on. It could be as "simple" as giving the design files to a company like TSMC or UMC and they give you back the bare wafers. Then you have to test them, cut them apart, package them, probably re-test, and finally label them. Of course there are other companies that will do most of that work for you, so all you get back are the tested chips ready to be put on a PCB.

If you have gotten to this point and it still seems like an ASIC is what you want to do then the next step would be to start Googling for companies and talking with them. All of those companies are slightly different, so it makes sense to talk with as many of them as you can put up with. They should also be able to tell you what the next step is beyond talking with them.

• Thank you very much for your detailed response. I will look into FPGA conversions. Thanks again, John – user5708 Sep 12 '11 at 1:15
• If you've read this answer, make sure to read the next answer too. You can get "normal ASIC" for a lot cheaper than $1 million if you need a very small quantity. – Roman Starkov Apr 18 '13 at 9:50 • I've heard the term "structured ASIC" used to describe FPGA conversions. – kjgregory Jul 2 '14 at 17:57 There are two major ways to get an ASIC made if you're looking at third party processes, such as IBM, ONsemi, STMicro, etc. The first is to work directly with the foundry (manufacturer), and the second is to work with a group that processes smaller orders. Working directly with the manufacturer, you are typically buying a production run for a particular chip. This will give you multiple wafers with multiple copies of a reticule. A reticule will typically be around 15 to 20mm2. You would be able to put whatever you want in that space, and you would then later divide the wafer into the individual designs. If you were making a production run of a single chip, your design would be tiled here. I don't know the prices for this, but it would probably run something like: $Cost = Masks + N \times Wafers$, where the masks are a dominant portion of your cost. I would estimate that for the latest 40nm processes, the costs start around$2 million.

If you are not looking for large volumes, or you are wanting to prototype a design, then there are companies that will buy a run from a foundry for one or two wafers, and then sell out space in the reticule. There are two major companies: MOSIS and CMP. They plan on buying only one or two wafers and a set of masks, so their production costs are basically fixed. Their prices are typically based on the size of your design in mm2. MOSIS doesn't publish their rates, but CMP's cheapest rate on a 0.35 micron process for 650 Euros/mm2. A non-trivial design will probably cost $3000 or more for 40 chips. The finer the feature size, the more expensive it is to make the masks. Another item to consider is that the design software needed to design and verify IC's is NOT cheap, unless you're doing it from a university setting. • @W5VO, Very well written. Thank you for bringing light, I put down an answer to help out, but yours is both clear and detailed! – Kortuk Nov 22 '10 at 1:45 • Thanks. It's hard to give precise answers to that question, especially since so many bits of the pie are covered by NDA's. Thankfully, CMP publishes their prices. – W5VO Nov 22 '10 at 4:22 • Thank you so much for answering! :) Btw, MOSIS has a form that you can fill out and it'll send you a quote estimate. I asked for 20 dies, 1mm square each with ON I2T100 (whatever it means, but it was the coarsest process in the list, 0.7um). The quote estimate was$10000. – avakar Nov 22 '10 at 9:17
• Try checking the ON C5N process. It is a straight CMOS process, with no fancy features. Their 0.7 um process has high voltage transistors and appears to be BiCMOS, which may bump up the price. Also, don't forget to add in packaging! – W5VO Nov 22 '10 at 13:03
• Some design software used to design and verify ICs is free. MAGIC, SPICE, IRsim, etc. See david.carybros.com/html/vlsi.html#design – davidcary Feb 7 '11 at 15:19

Although it's true that creating a chip is very expensive, TSMC and other fabs do provide "shuttle services" that put many devices from many people on the die and reduce the price significantly. I've even hear a company getting a few samples of it's devices for $1500, which is extremely low when you consider the alternatives. Before anything, it's best to implement as much as possible on an FPGA to ensure the logic is correct, etc etc. Now by end of 2018, a company is working on a platform "Itsy-Chipsy" (assuming a software tools collection plus fab services) to produce two prototype chips for about$400 at a 350x350um size which can fit 14000 gates. If the area size is further divide by 4, down to 170x170um, the cost would be about $100. The$100 price is based on the pricing of a 2x2mm chip by MOSIS, divided by 16, then by 4. The comments on the above hackaday page have more information but not all the details are figured out yet. They've visited the fabs and claimed to start a crowd funding campaign this year. This implies: with MOSIS for a chip of 2x2mm size, it costs $5000 to get 40 chips. One nice thing about it is that it's going to use all open-sourced tools, from ngspice.sourceforge.net, opencircuitdesign.com qflow and magic, and clifford.at yosys. Though no idea how those tools can be used with the libs, and what it takes. It will be interesting to see how that will work out. Looking at the CMP MPW price list of sept-18 in a pdf file: On a .35um CMOS C35B4C3 process, per mm^2 price is 650 euro, and the minimum area charged is 3.43mm^2. That's about 2230 euro, for 25 bare dies. This figure is more a reality as of today. A slide deck on nmi.org.uk from imec dated 2016 indicates a MPW example on .18um costs$25,000 for 40 dies at a minimum 25mm^2 area on the first wafer. Each additional 40 dies cost $2000. The presentation shows dedicated-mask costs too: For the same example, the first lot of 14 wafers cost$134,000 for 14x2945 dies. And each additional wafer of 2945 dies costs $1000. Additional per-die cost is$0.34. This $134,000 figure well matches the$100,000 number other few answers mentioned.

A 2013 thread on bitcoin.org titled "why is the asic development cost > 1M" shared a few numbers: [1] a long-wave receiver, involved 10 engineers for a year for $500k, two engineering tape-outs$250k, and $250k for 10k chips + verification and validation hardware. [2] The avalon bitcoin mining chip probably cost around$400k in total that was guessed based on the pre-order volume. [3] Some other common numbers for bitcoin mining are, ~150k USD for 130nm, 200-300k USD for 110nm, and ~500k USD for 65nm, as of 2013. Though those chips probably have a lower complexity.

Just wanted to add this in:

http://cmp.imag.fr/products/ic/?p=prices <-- CMP Price per mm^2 of the current price list is for 25 bare dies except for MEMSCAP and for TriQuint.

You can get a 0.35u (350nm) CMOS C35B4C3 asic, for only 650 Euro/mm2 (3), though their shipping prices are rather high (up to 100 euro's) and you have to pay extra if you want them to package it for you.

On the other end of the scale, you can get 28nm CMOS CMOS28LP for only 15000 Euro/mm2 (1) if you are doing less than 3 mm^2.

Let me be the first to state that custom ASICs are not for the faint of heart. Catalog parts are bad enough. For reference, a single mask at TSMC circa 2010 for a 0.18um BiCmos process was about $25k. Case study: I worked on a semi custom buck regulator chip for a customer. My company is a Fortune 100 semiconductor manufacturer. We charged something like$200k NRE, with the expectation of shipping at least $2 million. The customer set the max cost of the device to a certain price point, over which they would just use another solution. Also, after a small period of time, the device would not be exclusive for that customer. We figured it would be a slam dunk, just copy and paste side existing IP, then modify the design to suit. Unfortunately, there were issues in fab, assembly, qualification, test, characterization, design, and application that necessitated a respin of the device. We got it right in the second go round, but our customer had never done a custom ASIC before, didn't have great specs, and didn't really know what they were getting into. We basically did their entire system integration because they couldn't build a pcb to save their lives (heat, package selection, emi....) A choice is doing a FPGA conversion. Both Altera and Xilinx has that. I'd go with Altera. The prices are in the$100's k US.

• Xilinx's FPGA conversion is not a conversion, just a limited test of the same silicon. – Martin Thompson Nov 18 '11 at 14:42

Back when I was doing logic simulations for ASIC design, I heard $100,000 (US) as a price for a minumum size batch of a single ASIC design - but that was about 10 years ago, and probably only for one company. Have you considered using an FPGA? With an FPGA you can reorganize hardware components on a chip without the expense of creating your own chip. If you are in a university it's possible they have their own small FAB. The university I went to did. If they don't maybe you could talk to someone at a university that has a FAB and see if you could get them to make your chip, the fees would probably be lower that from a foundry. • yes, as I said, I'm not considering getting an ASIC, I'm just curious as to how much it costs. – avakar Nov 22 '10 at 21:47 Did you look at this? http://www.europractice-ic.com/ They have a full price list on the website. A similar service provider, that accepts small projects, is MOSIS (https://www.mosis.com/). They also offer additional services and provide software licenses on the need. In general, to have the full price you need to submit a list of services that you need and they will be more than happy to provide a quotation. Beware that the fabrication cost is only a fraction of the total cost of an ASIC. A significative part of the final cost is taken by licenses, test, qualification and packaging. In practice, you might spend between 5000€ and 10'000€ for a relativly simple analog asic in 0.35µ technology, including packaging but without any quality assurance (no services, no IP blocks, no test). • Since the question is "how much does it cost", rather than "who provides such services", I would suggest including a baseline price and a description of what that would include. Something like "If one has files in XYZ format laid out in a pre-set 1mm^2 44-pin footprint using two-metal half-micron technology, one can get PLCC-44 mounted prototypes for$NN per group of four." If you could add such information, that would be helpful. – supercat Sep 18 '15 at 15:23
• It would be completely useless because: 1) The unit price is calculated differently by different manufacturers 2) The unit price varies with the chosen technology 3) The unit price varies with the quantity, packaging, additional services (test, qualification, etc...) Without having more data, it's impossible to estimate a price. – ingframin Sep 2 '16 at 15:12
• the link to pdf file is broken now. – minghua Jan 6 '19 at 5:45
• @minghua fixed! – ingframin Jan 8 '19 at 9:26
• Links are broken again. In general, copy the TLDR of the link to answer the question, because link rot is a real and common thing. – Jon Watte May 19 at 18:58