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I was working with the simulation I attach below. While testing my simulation I was confused when I observed a short circuit on the half bridge, and it did not get better when I added extra deadtime on the control signal. I don't understand the reason of short time peak currents. I am attaching graphs of the simulation outputs.

Gate voltages of HIGH side and LOW side

Current of H-Bridge

Simulation Circuit

EDIT: Lowering the bootstrap cap (not too much because the MOSFETs caps need to be charged for the desired frequency and duty cycle) is the key to decreasing peaks on the current. In the given circuit I added inductances to reduce the effect of drain-source capacitance.

new circuit

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  • \$\begingroup\$ Cross conduction? Post HO and LO oscillograms, ideally also M1(GS) and M2(GS). \$\endgroup\$
    – winny
    Feb 29 at 16:02
  • \$\begingroup\$ First graph is HO and LO oscillosgram. \$\endgroup\$
    – MSB
    Feb 29 at 17:01

1 Answer 1

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I don't understand the reason of short time peak currents

Each time you deactivate a MOSFET, it's internal drain-source capacitance has a very low voltage across it. This is because the associated MOSFET was previously activated. Some short time later you activate the other MOSFET and that turns on rapidly and, of course, has to charge up to the full power rail the deactivated MOSFET's drain-source capacitance. That can generate a huge pulse of current.

However, parasitic inductances in power rails (just a few nano henries) can somewhat alleviate this situation. There is also the parasitic inductance of the MOSFET that is being activated to alleviate the situation and, what you find is that you won't have a problem in reality (in most cases).

You might also try adding an impedance in series with your 311 volt supply so that it is more accurately represented. This will reduce the problem too.

BTW your circuit shows a half-bridge and not a H-bridge.

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  • \$\begingroup\$ Thanks for response sir. I am adding a nano henries inductance on power rail. When I select a low Gate Capacitance MOSFET for Half-Bridge Circuit the peak current getting a little better. But can't solve the issue. \$\endgroup\$
    – MSB
    Feb 29 at 17:00
  • \$\begingroup\$ You can try maybe a few tens of nano henry. You should also consider the line impedance that feeds the 311 volts. I bet there's several tens nano henries and a couple of ohms. Sometimes you just have to bite the bullet and try a few things out. It's not having a low gate capacitance mosfet that is the problem; it's the drain-source capacitance that is the issue. \$\endgroup\$
    – Andy aka
    Feb 29 at 17:36
  • \$\begingroup\$ I make lower peak current to 6. With resize Cbootstrap. And lower Supply of IR2110 to 12V. Higher Rgate(on) and Rgate(off) replacement. Adding a reverse recovery diode. \$\endgroup\$
    – MSB
    Feb 29 at 17:46
  • \$\begingroup\$ @MSB that sounds a whole lot better. Regarding your edit to your question. Can you add a few words indicating that it was made following a discussion with an answerer? Then, when someone random comes along they won't be confused. \$\endgroup\$
    – Andy aka
    Feb 29 at 18:01
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    \$\begingroup\$ @msb yes it's one of those things that has to be acceptable. Engineers have very little choice other than facing the fact that rapidly charging or discharging the drain source internal capacitor is inevitable. I mean that when the MOSFET activates, it also discharges it's own DS internal capacitor and we have to believe that the manufacturer has designed it properly! \$\endgroup\$
    – Andy aka
    Feb 29 at 18:32

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