# Why did my DC/DC Buck Circuit fail?

I'm in the process of debugging a PCB I made. On this board, a 24V input feeds through a DC/DC buck circuit (based around the TI TPS54202DDC) to output 11V, then an LDO to output 9V (to ensure a very stable 9V, I didn't want to convert directly to it).

When I plugged in the power supply, the TPS54202DDC popped immediately. I've provided my component selection logic below, have I made any mistakes there? I'll also include a picture of the layout on the PCB, though I'm relatively confident in it.

First, the datasheet for the converter - I'll include some screenshots below explaining my logic that contains excerpts: https://www.ti.com/lit/ds/symlink/tps54202.pdf

Basic specs:

• Input Voltage: 24V (may not be rock solid, but I'll use a V_in(max) of 25V)
• Output Voltage: ~11V (Just need adequate voltage that an LDO to 9V has plenty of headroom, but isn't burning too much voltage as heat)
• Output Current: ~100mA, I'll spec for ~150mA to be safe.

The datasheet suggests that all of these are well within the range for the selected converter. F_sw comes from the datasheet at ~500kHz.

8.2.3.1 Input Capacitor Selection

$$\Delta V_{\rm in} = \frac {0.25 \cdot I_{\rm out(max)}} {C_{\rm bulk}\cdot f_{\rm sw}} + \left( I_{\rm out(max)} \cdot {\rm ESR}_{\rm max} \right) \tag{4}$$

I chose a ceramic 10μF 50V capacitor, and a parallel 0.1μF capacitor as recommended by the datasheet. The ESR on ceramics should be basically negligible, so I calculate a $$\\Delta V_{\rm in} = 7.5{\rm\,mV}\$$, which ought to be plenty small.

8.2.3.2 Bootstrap Capacitor Selection

The datasheet just says 0.1μF, very straightforward. To be safe I kept it 50V tolerant.

8.2.3.3 Output Voltage Set Point

$$R_3 = \frac {R_2 \cdot V_{\rm ref}} {V_{\rm out}-V_{\rm ref}} \tag{6}$$

$$V_{\rm out} = V_{\rm ref} \left(\frac{R_2}{R_3} + 1 \right) \tag{7}$$

According to section 6.5, $$\V_{\rm ref}\$$ can vary from a minimum of 0.581v to a maximum of 0.611v with an expected value of 0.596v. Using the expected value of 0.596v and an R2 value as directed by the datasheet, which states "Select a value of R2 to be approximately 100 kΩ", we get a value of 5.73K for R3 - I selected a 5.76K which should result in $$\V_{\rm out} = 10.94V\$$ - close enough.

8.2.3.4 Undervoltage Lockout Set Point

Ignored; left EN floating.

8.2.3.5.1 Inductor Selection

$$L_{\rm min} = \frac { V_{\rm out} \left(V_{\rm in(max)} - V_{\rm out} \right) } { V_{\rm in(max)} \cdot K_{\rm ind} \cdot I_{\rm out} \cdot f_{\rm sw} } \tag{8}$$

The datasheet tells us to use a $$\K_{\rm ind}\$$ value between 0.2 and 0.3 - I selected 0.3, as it was what they used in the example (and the text mentioned it was appropriate for low-ESR output capacitors, like I'll be using). Our minimum inductor value is 273μH. If we use slightly more rounded values - 11V for output, 24V for maximum input voltage, and 100mA current, then we get a minimum inductor value of 397μH. The datasheet also says "Smaller or larger inductor values can be used depending on the amount of ripple current the designer wants to allow so long as the other design requirements are met. Larger value inductors have lower AC current and result in lower output voltage ripple. Smaller inductor values increase AC current and output voltage ripple."

Because I want to minimize ripple (I want a very stable output voltage, hence the LDO stage that follows this DC/DC) and due to what I could find, I selected a 470μH inductor.

8.2.3.5.2 Output Capacitor Selection

$$C_O > \frac { 2 \cdot \Delta I_{\rm out} } { f_{\rm sw} \cdot \Delta V_{\rm out} } \tag{11}$$

To have at most 100mV of output ripple for a 150mA step, equation 11 tells us we need at least 6μF of output capacitance. In general, more capacitance = less ripple, and I was already using a 22μF capacitor elsewhere on the board so I used it here, too.

This will give us a crossover frequency of 16.4kHz, according to equation 14, which is below the recommended 40kHz.

8.2.3.5.3 Feed-Forward Capacitor

$$C_6 = \frac{1}{2\pi\,f_0} \cdot \frac{1}{R_2} \tag{16}$$

We'll also use a 97pF capacitor as feed-forward "To improve the phase boost". I selected 100pF.

After the DC/DC Buck, I use an AMS1117 to drop the voltage to 9V. It has a reference voltage of 1.25V, so for 9V output I used a 120/750 resistor divider, which should provide 9.0625V (close enough for my purpose, so long as it's stable).

I was careful with layout on the PCB to minimize loop area, and came up with this:

Immediately upon plugging in the power supply (confirmed 24V), the TPS54202DDC released the magic blue smoke. Is there anything I've done that's obviously wrong?

• Ceramic input capacitors strike again! This is a duplicate post, but one of the cases where it's harder to search for (as the asker), and faster to answer than to search for a suitable duplicate. Feb 29 at 20:45
• @Helpful Oh they are not an issue. The inductance you use to feed them with will be an issue. A ceramic capacitor is a short at AC. Rule of thumb: hook up wire is 10nH/cm. 50cm of that is a nice 0.5uH. What do you suppose happens when you connect a 0.5uH high-Q inductor into a short, and then release the short (as the capacitor charges up)? Yeah, a destroyer of worlds happens (in memoriam Jim Williams) :) Feb 29 at 21:05
• Kudos for putting everything into the question ahead of time. Good job! Feb 29 at 21:06
• Feb 29 at 21:34
• @Helpful - Re: "who is Jim Williams?" The late Jim Williams was a well-known analog designer, who died in 2011 (see this article for more about him). And then Bob Pease, another well-known analog designer, died in a car crash, coming back from a memorial service for Jim's death :( Mar 1 at 17:32

Any appreciable wire inductance from the 24 volt source is going to cause a ringing spike of anything up to twice 24 volts at the input to the chip and, that chip has an absolute maximum rating of 30 volts. I would use something like a 26 or 27 volt TVS across the input supply capacitors to prevent this type of problem.

• I've got some replacement chips coming, and I'll give this a shot for sure. Feb 29 at 20:57
• @Helpful And ramp up that supply voltage slowly by hand! Don't use a brick. Start with a lab/bench power supply, set current limit to 0.5A, and ramp up the voltage from 0V up to 24V by hand. Feb 29 at 21:02
• In practice, users might just be hotplugging - so I need to make sure the design is capable of handling that. @Kubahasn'tforgottenMonica (also thanks for the question edit, you made it MUCH prettier). Feb 29 at 21:03
• Keep the feed wires twisted to minimize inductance is always a good idea even if just to reduce switching regulator emissions. Feb 29 at 21:03
• @Helpful: Starting with limited current and low voltage allows you to find things like short circuits without permanent damage. Of course it’s not a permanent solution ;) Mar 1 at 8:06

If you are absolutely sure you soldered it the right way around, cause of death should be overvoltage as per Andy's post.

You can add a TVS and/or an aluminium electrolytic of a few hundred µF at the input. It should be a cheap general purpose cap with a good amount of ESR to damp the resonance between your input caps and the wiring inductance.

Note the inductor rated current is quite low (230mA) and its saturation current is unspecified, while the chip has a current limit of up to 3.9A on the high side switch... so I wonder if the chip's internal overcurrent protection will be fast enough to save the MOSFET if the output is shorted. It will probably go into thermal shutdown.

Here's an example of inductor current when it saturates, from this appnote. When the core material saturates, the inductor becomes more like an air core inductor. So it loses most of its inductance and current rises much more quickly (di/dt = V/L) which is visible as a huge spike in inductor current. Power dissipated in the FET is RI² so it rises very fast. Then it's a race between the reaction time of the overcurrent protection in the chip and the MOSFET's temperature.

Although in your case, with the inductor having a thermal limit of 230mA, it probably has enough internal resistance to save the MOSFET... by overheating and desoldering itself from the board, as the buck chip is still capable of feeding several amps into this inductor.

Using a chip with a high current limit means you need the inductor to not saturate at the limit (or at least not saturate too much)... and also not burn... but for a low current converter you need a high inductor value (otherwise it will be in cycle skipping / powersave mode all the time and you get high ripple and lower efficiency). So using a high current chip for a low current application forces an impractical inductor (470µH rated for a few amps, which means large and more expensive).

If you use a chip rated for 200-500mA output current it will have much lower current limit so you can use a physically smaller inductor with a lower saturation current. You could use a chip that allows you to set maximum current with a resistor, but these usually require an external FET.

Note AMS1117 is not compatible with ceramic caps on the output, for stability it needs high-ESR tantalum cap, or plain old aluminium (general purpose, not low-ESR). Also its main selling point is low cost, not exactly high performance, transient response is slow and PSRR at the frequency of your switcher is unspecified.

• Yes, "Iout" in the calculation should be the regulator's rating, not what's being used nominally; the fixed internal compensation won't be correct, either. Values can simply be chosen from the recommendation table (datasheet page 17), for which the 12V case is close enough, just tweak the feedback resistor(s). Feb 29 at 20:50
• @Helpful Compensation relates to stability (it may oscillate) and output impedance; even if not oscillating, it may have excessive overshoot, or go unstable with certain loads. Try a load-step test. Feb 29 at 21:14
• @Helpful Like I said, regulator rating, not nominal operating current. It may peak up to rating during startup, inrush or fault conditions anyway, and you have no way to restrict its operation to a lower nominal value (you could with a controller, though). The inductor therefore needs the 2A+ rating as well. Regarding ESR, you can hack a small resistor in series with the ceramics; probably 0.1-1 ohm is adequate. Feb 29 at 21:23
• @TimWilliams Oh! You're saying in Equation 8, the I_out is not up to me, it's a worst-case/maximum for the chip - that does resolve the discrepancy; I wish that was called out a bit better in the datasheet. When I run the numbers with a 3A max output current (I_(Lim_LS)) I'm much closer - then some additional inductance above that minimum helps (obviously to a point) efficiency/stability. Is that right? Feb 29 at 21:29
• Yes using a chip with a high current limit means you need the inductor to not saturate at the limit (or at least not saturate too much)... but for a low current converter you need a high inductor value (otherwise it will be in cycle skipping / powersave mode all the time and you get high ripple and lower efficiency). So using a high current chip for a low current application forces an impractical inductor (470µH for a few amps, that's going to be larger and more expensive). Feb 29 at 22:45

My concern is that even if you make this work, you will be disappointed with the noise performance. I would use a different part with lower peak current because it will be better for noise, but what follows assume you stick with this one.

You should never place the inductor on the other side of the board unless you have a lot of experience with this sort of thing and understand the tradeoffs involved. The single noisiest part of a DC/DC is the SW node (this is all the copper that connects, in your case, pin 2 to the inductor). A close second is the VIN node which is essentially part of this same circuit when the high side FET is turned on. EDIT: I realise now that the inductor was not on the other side of the board - but the real issue is tunneling SW node through vias, so the comment stands.

You want low inductance on the VIN side; you already have a big cap and so adding a bit more capacitance by using lots of copper to connect the cap to VIN/GND pins is OK, so long as it reduces the inductance.

You want low capacitance on the SW side; otherwise you create a C-L-C like structure with the FET in the middle and whenever the FET switches on you'll get current washing back and forth through the parasitic inductance of the copper, leads, package, etc. So as a rule, use the minimum copper to connect SW to the inductor (minimum being something that will comfortably carry the peak current, in this case 3-4A I think).

The best way to minimise all the noise that these two bits of copper create is to move the inductor as close to the package as possible and then place the VIN cap as close as possible without compromising the inductor.

Don't forget that the copper carrying the positive half of the signal needs to be mirrored by copper on the GND side to carry the other half.

This package seems to have ignored this issue, but it's still possible to do something not too awful (it's never going to be "good").

This is a 2 layer with solid GND on L2 (not shown). The inductor is 12.7x12.7mm - that should be big enough to get a shielded 470uH inductor with adequate saturation current for your typical use case and beyond - you would need to test short circuit performance to make sure the DC:DC survives.

The GND return current for VIN is sub-optimal, but that's the compromise.

The other option is to switch to something like a 1210 VIN cap. You may or may not get better results with this - very hard to say. If you do a new PCB, you could happily include both options and see which one works best.

I am assuming a solid GND under all these designs. You could flood GND on L1 but I wouldn't, at least not to start with.

I deliberately keep the FB filter over on the far side of the chip away from noisy SW/VIN nodes.

Given the relative size of inductor to everything else, placement of VOUT cap(s) isn't going to do much - for a smaller inductor I would try to place them parallel to the inductor to minimise the size of the VIN-VOUT loop (the ripple current flows in this loop) - but we're beyond that here :-)

Also I am deliberately not using thermal relief on the SMD pads - this assumes you will always oven solder, where it doesn't matter so much for this size of component. I've only got copper pours where I think it will help matters.

Try to keep the inductor physically as far away from the noise sensitive circuit as possible - even a shielded inductor will produce an alternating magnetic field above the PCB (and below if you don't have solid copper underneath it - typically GND).

Finally, your LDO isn't going to do much, if anything, with the VOUT ripple current. As you only need 200mA approx I suspect you can design an RLC filter that will carry 200mA DC comfortably and provide plenty of attenuation at 500kHz. Probably be a couple of 0805/1206 parts (one L with non-zero DCR forming the RL and one C). Tiny compared to the enormous inductor :-)

• This is really well thought-out, thank you for taking the time to respond! In section 10 of the datasheet, the example it gives shows the switching node traveling through vias onto an inner layer. You're suggesting that's not optimal? To clarify, my inductor and switching controller are both on the same side of the PCB – it sounded like you were strongly advocating for that. What do you think of my layout presented in a screenshot at the bottom of my question? Mar 1 at 21:20
• Apologies for misreading your layout. Even so I think routing that SW node through inner (or rear) layer is bad news. It's going to create a load of unwanted coupling to other layers and signals. The exception would be if it's a 4 layer board and this signal is on L2; that's because you have GND on L1. I still wouldn't do it though ;-). What I am actually advocating against is placing vias in SW node; once you've done that, it doesn't make it better/worse to have the inductor on the other side. I'll edit my answer to make this clearer and remove my misunderstanding. Mar 2 at 18:15
• Re the rest of the layout, I don't think you need the small cap and I would much prefer to see the big cap as close to the power/GND pins as possible. I think you will see a lot of GND ripple on the GND pin, especially with SW tunneling under it. As per my answer I would use solid connects for planes/SMD pads rather than thermals .. let the current find the best path possible. I would separate the FB circuit from the rest - connect to VOUT with single thin trace, don't share GND copper with VOUT cap - give the FB circuit a via to GND plane. Mar 2 at 18:26
• And don't underestimate the noise that the inductor can create with the EM field it creates .. so use a shielded one and keep it far away from noise sensitive circuits. Mar 2 at 18:29