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I am doing the PCB layout of a DDR3 U-DIMM and I have run into a perceived gap in the JEDEC DDR3 DIMM standards and am hoping to get some input from a DDR3 SME who could clarify the Address/Control reference plane.

Long story short, I am designing a U-DIMM card to accommodate parts testing of a fully packaged DDR3 memory module. There is a 199 pin BGA memory which I am going to be testing using a Zynq 7000 SoC on a custom Dev board with a 240 pin DDR3 U-DIMM slot. Another engineer previously did a test with the same memory using a COTS Zynq 7000 dev board using a SO-DIMM form factor for the test board. So I am referencing his design, which has lead me to reference both the U-DIMM and SO-DIMM JEDEC standards.

The gap I have run across surrounds the reference plane for the address/command group's transmission lines. The SO-DIMM JEDEC standards specifically mention these being run adjacent to VDD in two places.

  • JEDEC Standard No. 21C: 4.20.21 - 204-Pin EP3-6400/EP3-8500/EP3-10600/EP3-12800 DDR3 SDRAM 72b-S0-DIMM Design Specification: Section 5.3 Signal referencing guideline
    • Specifies Vdd as reference for Clock nets, pre/post-register address and command nets in a table
  • JEDEC Standard No. 21C: 4.20.18 - 204-Pin DDR3 SDRAM Unbuffered SO-DIMM Design Specification: Section 6. SO-DIMM Wiring Details -> Cross Section Recommendations
    • Notes, in an introduction, that "All data is referenced to Vss and all address/command and clocks are referenced to Vdd."

The U-DIMM standard doesn't include any details about reference plains at all.
JEDEC Standard No. 21C: 4.20.19 - 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification
Skips/leaves out the Signal referencing guideline section, and leaves out mention of referencing in the Cross section recommendations section.

At this point I would speculate that the stricter SO-DIMM specification (thinner stackup -> fewer layers, smaller board) lead to the need to specify how to run something adjacent to something other than VSS, and if you have to do that it should be Address/Control <-> VDD. Where the less strict full size DIMM physical size (thicker stackup -> more layers, larger board) should not need this accommodation, so it isn't mentioned. However, the pinout of the 240-pin places all the Vdd supply pins adjacent to the address/control group, rather than Vss.

The ultimate guidance is whether my DIMM card should have address/command nets routed adjacent to a Vdd plane or a Vss plane, and whether the Zynq 7000 SoC dev board should have address/command routed adjacent to Vdd or Vss. I couldn't find details about how PC motherboard manufacturers do this.

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Someone over on Redit was able to provide some insight. https://www.reddit.com/r/PCB/comments/1b47hjm/ddr3_udimm_signal_reference_plain/

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