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I am trying to understand how alternate functions work at the register level for the GD32 microcontroller. For example, in the case of the GD32F103, there are several alternate functions available for pin PA1: USART1_RTS, ADC12_IN1, TIMER1_CH1, and TIMER4_CH1. From the GD32F103xx datasheet:

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The user manual states that to choose an alternate function, we should set 10 or 11 in the CTL register (GPIOx_CTL0). However, I don't understand which specific function will be assigned to PA1: USART, TIMER1, or TIMER4. From the GD32F10x User Manual:

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Could someone with experience with the GD32 provide some guidance?

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2 Answers 2

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Step 1 is to configure the pin using the GPIOx_CTL0 and GPIOx_GTL1 registers, as you know.

Step 2 in many MCUs, is to select which alternate function you wish to use, from within a GPIO or PINMUX type peripheral... I've tripped on this before with the STM32F103 family (very "closely related" to the GD32F103), and it seems neither of them support this - instead the output signals are enabled from the peripheral's side (I don't know what happens if you enable two, "be careful"?).

I haven't actually used the GD32F103, but I believe you can simply set GPIOA_CTL0.CTL1 and GPIOA_CTL0.MD1, then:

  • For USART1_RTS: set USART_CTL.RTSEN
  • For TIMER1_CH1: set TIMER1_CHCTL0.CH1MS[1:0] to output, and then set TIMER1_CHCTL2.CH1EN to enable that output
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However, I don't understand which specific function will be assigned to PA1: USART, TIMER1, or TIMER4.

If there are multiple peripherals configured to use PA1, their outputs are all ANDed together internally. In practice, this means that, if you aren't using one of these functions (e.g. if you aren't using the timer channels), that peripheral will output 0 and will be ignored.

The AFIO control registers can also be used to remap some of those functions to other pins. (In particular, USART1_RTS can be remapped to other pins, but note that it'll move some of the other USART pins as well.) If these functions are remapped, they no longer drive PA1.

A lot of this mess is inherited from the STM32F1 series, which the GD32F103 is a clone of. Newer STM32 (and GD32) families use a tidier GPIO system where each pin can have its alternate function selected individually from a set of options.

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    \$\begingroup\$ Ugh, you're right. Corrected. \$\endgroup\$ Commented Mar 2 at 1:33
  • \$\begingroup\$ "their outputs are all ANDed together internally" ... sorry to pick on you again, but they're ORed? Can you quote documentation to back this up, or is this from playing / experience? (I thought I managed to find details in the STM32F103 docs previously, but can't right now... it makes me nervous either way!) \$\endgroup\$
    – Attie
    Commented Mar 2 at 1:41
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    \$\begingroup\$ Experience and a bit of guessing. ST recommends (in a footnote under the pin definitions, of all places) that you only clock one of the peripherals which would drive a pin. In practice, if you clock more than one anyway, they behave like the outputs are ANDed, which is almost certainly what's going on internally. \$\endgroup\$ Commented Mar 2 at 1:54
  • \$\begingroup\$ Interesting, thanks! ... I wonder how they expect these parts to do anything complex / useful if you're supposed to choose between TIMER1 and USART1 for example. \$\endgroup\$
    – Attie
    Commented Mar 2 at 2:31

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