# MOSFET Driving for a Dump Load Resistor within a wind turbine

I am currently designing an AC-DC rectifier for a 6 kW small-scale wind turbine. As part of this setup, I intend to integrate a dump load resistor to regulate overvoltage. When the DC voltage reaches 500 V, a switching mechanism will activate to safeguard the inverter and allow the dump load to dissipate excess energy.

My plan involves employing a MOSFET-based switching system. However, I'm uncertain about the optimal circuit design for this task. My initial approach is to utilize a microcontroller to control a low-power MOSFET, which in turn will drive a high-power MOSFET using pulse-width modulation (PWM). Despite this, I'm encountering confusion regarding the most suitable circuitry configuration, particularly regarding N-type versus P-type MOSFETs, loading on the high side or low side. (The peak current is expected to be 20 A.)

To illustrate, I have included a simple block diagram for reference.

You don't say how much is required to dump (is the inverter ever inoperative while the turbine is at nominal speed? is it ever overspeed?), so I will assume the total given. You can adjust values as needed if this is not the case.

6kW at 500V is 12A. 500V / 12A = 41.667Ω. You will need a sizable resistor (or array thereof) to dissipate this, rated 6kW in total, obviously.

The value can be lower, to provide a higher maximum dissipation capacity, and PWM used to achieve a higher average value as needed. Values from say 20 to 40Ω would seem reasonable here.

I'm also assuming nothing will mind ripple on the DC link, so that a PWM solution is acceptable.

The missing variables are the acceptable change in voltage (ripple peak-to-peak), frequency, and the value of that capacitor there. I will assume frequency near or above mains, and ripple ca. 10%.

I've previously built a worked example of such a circuit, for ballasting a 24V (nominal) supply to 29V at up to 2kW input. Schematic: https://www.seventransistorlabs.com/Images/ShuntBallast.pdf

In this case, I used an enable switch, and common TL431 voltage reference as comparator. In your case, this can most likely be wired always-on, and either a low-voltage or auxilary supply used to power it, or a lower current (TLVH431, etc.) model used to save current consumption while deriving supply directly from the 500V rail.

R1 supplies bias current to IC1 and Q2, regulated by a zener D1. These can be replaced with a high-voltage regulator, transistor follower or cascode to minimize excess current draw and increase compliance range, or an aux. supply can be used directly, as mentioned.

As shown, maximum current consumption is about 5mA, set by R5 and R9. A little extra is drawn due to gate charge, which is reduced by choice of low operating frequency, and gate drive peaks are supplied from C4. To reduce bias current, a complementary emitter follower (replace D2 with an NPN) might be used to amplify Q2's pull-up current, and a low-current TL431 can be chosen, allowing larger values for R2 and R5.

For a max. 500V supply, assuming a 1mA 2.5V TL431, you would need R1 < 490kΩ, R8 < 20k, R5 < (VCC - VBE - 2V) / (1mA), and R9 depends on required drive strength.

R4, R7 and R8 determine the rising and falling threshold voltages. Notice, when inactive, R7 is in series with R9, and this equivalent is in parallel with R8. This divides with R4, and the divider voltage must equal 2.5V when the input equals the 500V rising threshold. R4 and R8 will dominate, so that R4/R8 ≈ (500V - 2.5V) / (2.5V), but R8 will be slightly larger, or R4 slightly smaller, to account for the loading effect of R7 + R9. The falling threshold is determined by R7's effect upon the divider: we choose a value such that, for gate-on voltage applied to the resistor, the threshold drops by the hysteresis band, 10% or 50V, or 0.25V at the divider node. (Notice we can consider R4 and R8 in parallel, as a Thevenin equivalent, for these purposes.)

MOSFET choice and switching frequency determines gate drive requirements. Presumably, one would like to avoid a costly heatsink here, so choosing transistors for a modest power dissipation, say 20W (enough to require a small to medium heatsink, or chassis mounting, but no particularly special considerations beyond that), seems prudent. Based on conduction loss alone, at 12A, this is 0.14Ω max RDS(on), and a rating over 600V should be used. 600-750V transistors are cheap and plentiful, though cutting the rating a little close (more on that in a bit). Examples include Infineon IPP60R099P7XKSA1, Vishay SIHG105N60EF-GE3, etc. Typical parts have gate charge in the ballpark of 40-100nC.

Switching frequency is controlled by link capacitance. In my example, an overcharged or disconnected battery can be assumed a fairly high impedance, and local capacitance can be assumed to dominate; the source can be assumed high impedance as well, worst-case a current source. Therefore, local capacitors were added, which also reduce ripple current throughout my battery system. We can assume the capacitors charge linearly while the dump is inactive, and discharge exponentially while active. In the small ripple approximation, the discharge can be assumed linear as well, and we have:

$$F_\text{sw} = \frac{I_\text{src}}{C \, \Delta V } \left( 1 - \frac{I_\text{src} R_\text{L}}{V_\text{max}} \right)$$

If we choose this as a couple kHz, and use a middling to low value load resistor, we have a minimum C around 60µF.

Likely, an inverter needs more for multiple reasons (generator or mains-frequency ripple handling, ripple current rating, to reduce dissipation, etc.), so this isn't a problem, and a lower Fsw can be expected.

Suppose C = 1mF and RL = 20Ω; we can also choose a lower ΔV say 20V. We then expect Fsw around 300Hz.

The gate switching speed should be fast enough to keep switching losses acceptably low, while not causing problems with nearby circuitry -- the resistors and wiring will be quite large, and hard-switching into them would be an EMI nightmare for nearby circuitry. For a first guess, we use the triangular approximation:

$$P_\text{sw} = 0.5 V_\text{off} I_\text{on} t_\text{sw} F_\text{sw}$$

where tsw is the total commutation time (rising plus falling).

Real MOSFETs have extremely nonlinear Coss (that is, dependent on VDS), in such a way that switching losses tend to be reduced significantly (but can also be many times more, in hard-switched half-bridge for example), relative to this calculation -- hence just a first guess. If we say 10W of switching loss, we have tsw < 11µs, very reasonable.

Gate current is $$\I_G = \frac{Q_G}{t_\text{sw}}\$$, and for typ. 100nC and 10µs, we need 10mA. Probably boosting this to 100mA would be safe, without inviting EMI issues, and such currents are easily obtained from general-purpose transistors like MMBT3904/6, BC847/857, etc.

The gate resistor R3 and R6 values are noncritical; choose values comparable to gate drive speed, i.e. VGS(on) / IG(pk), particularly when parallel transistors are used. (It sounds like this probably won't be required here; in my case, paralleling was convenient both to respect ratings of the transistors I had on hand, and to wire the resistors separately (which were also on hand) in case I wanted to do anything with the circuit at a later time.) So, 10-100Ω will be fine.

In contrast, I know from experience, transistors of this rating can switch quite quickly indeed, even with fairly large gate resistances; Coss and Crss drop so sharply above 20V or so, that Miller effect is nearly obviated. I would actually recommend considering / testing out, some added impedance, such as an R+C snubber between drain and gate. Typical values might be 22-100pF and 1kΩ. This ballasts the otherwise nonlinear capacitance, setting a maximum drain rate-of-change (dV/dt) while increasing QG modestly.

Finally, some transient protection is likely desirable. The resistors will be wirewound type, having noticeable inductance (10s µH perhaps). MOSFETs of this type are not rated for repetitive avalanche, so it must be handled externally. Probably, turn-off time can't be made quite slow enough to dissipate this power reliably as channel power (which is a safe route for dissipation, at least in short (~µs) bursts as here; avalanche current is dissipated differently, in a way which gradually damages the device), so a TVS clamp diode as shown is effective mitigation.

If the resistors plus wiring amount to say 10µH total, the peak energy is (10µH)(12A)^2 / 2 or 720µJ, repeating every 300Hz, or about 0.2W. Even a small TVS will dissipate this handily; likely a somewhat larger type will be chosen for a sharper knee, or other reasons (transient voltages on this rail have not been mentioned; direct lightning strike of a windmill I suppose might be a motivating concern, to this end). Such voltages are not usually available, but series connections are perfectly suitable, and SMCJ160A × 3 might be a candidate. Downside: the clamping voltage would be over 777V, too far into the MOSFET rating to be comfortable. I would suggest choosing a higher rated device, then.

A larger TVS, just to further confine the peak voltage, or a MOV to reduce cost (at expense of higher peak voltage), or an RC or RCD snubber, are also options.

Regarding MOSFET type and position, no requirements for low-side load were indicated, so there is no benefit to high-side gate drive, or a P-channel MOSFET. P-ch devices of suitable ratings are also few and far between, and perform quite poorly in comparison (not poorly enough it would be a problem here, but more to explain their general scarcity). (Specifically, the dynamic figure-of-merit is about 2.5 times poorer for P-ch than N, more or less a direct consequence of electron vs. hole mobility in Si.)

Probably, a practical design requires basic or reinforced type insulation from the chassis for safety or reliability purposes, and a captive element such as a load resistor can be freely wired either way; we prefer low side, then, to use a common-ground control/drive circuit.

A microcontroller is not required, either; nor would it be recommended, for reliability reasons.

Reliability diversion:

Proving the correctness of software, let alone of unknown or poorly documented (IC) hardware, is arbitrarily difficult; proving the correctness of analog circuitry -- though it may seem complicated or unfamiliar to some practitioners, is however far more tractable.

A simple function such as this, is easily realized from simple hardware -- transistors and simple ICs. They are cheap and readily available, well understood, and can be obtained in high-reliability and traceable versions as well, if one really needs it (e.g. MIL spec, aerospace, life support, etc.).

If needed, a digital input, or monitor output, could be added to the circuit; Q2 basically serves as a high-voltage logic inverter with '1' or 'Z' output (and 'L' state provided by R9), and logic functions (mask/enable, force-on, etc.) could be added with CD4000 series logic, or by using additional BJTs (MML ("Mickey Mouse Logic"), as Horowitz and Hill put it). A monitor output can easily be added by tapping R9 into a divider for logic-level (say 3.3 or 5V) output; a current sense shunt resistor could also be added under the transistor(s) for monitoring the load resistor.

More broadly speaking: I'm a strong proponent of the hands-off approach to digital control. Make a robust, responsive, but otherwise fairly dumb, analog circuit to control the nuts-and-bolts of the power switching system -- indeed, the dumber it is, the easier it is to design and verify, through inspection, simulation and testing. But only so dumb to a point: it must handle all foreseeable operating conditions and failure modes, and save enough time for the digital control to respond to them. Meanwhile, the digital control can be arbitrarily complex, while taking the time to prepare results -- which can be as straightforward as DAC outputs for voltage or current operating points at very modest sample rates (10kS/s, say?), plus some logic pins to direct machine state. It may be an old archetype (digital/hybrid systems dating back to the '70s and even earlier, simply didn't have CPUs at all, that could run more than a few MHz, let alone produce accurate timings or manipulate high sample-rate data streams by themselves!), but simplicity is a strength

It is, of course, possible to build a direct digital control circuit -- but it is exponentially more difficult to guarantee, or prove, operation. Most of the time, it's trivially impossible, simply because the devices aren't well enough documented by the manufacturer. Even when the logic diagram is under user control (e.g. FPGA), confirming and proving that design is a big challenge, let alone when CPU caches and concurrent threading get involved in the software case.

Not that this function requires complicated software, or anything -- but the problem isn't software complexity, it's the existence of software at all, and the unknown platform it's running on. You can only be as confident in the function and reliability of the overall system, as its weakest link -- and, at least personally speaking, I'm nowhere near a good enough coder to feel comfortable doing such a thing. (For reference -- not that it really means anything just to say so -- I would consider myself experienced at C. I probably have an average bug rate (to the extent one can imagine such a measuring that). The main thing is I'm rather slow at development. Hardware is more my specialty.) I have done a few power controls in software at this point, but I don't make a habit of it.

Anyway; perhaps these points are already well known and understood, and I'm preaching to the choir (excellent!). If not, perhaps there are other places in the project where such warnings might be profitably applied? Or, perhaps the project is too far along development to make such sweeping changes, in which case, this can still serve to guide the next project that comes along. Whatever the case, best of luck!

As far and N vs. P, you'll quickly find that the choice has been made for you. It will have to be N-channel. Availability.

The part will also require a fairly substantial heat sink to handle 20A continuously unless it's rather hefty and thus expensive. High voltage MOSFETs have relatively high Rds(on) for their die size.

It might be preferable to use a relay- you might be able to find a DC rated relay that was developed for EV applications. General purpose relays are not suited for switching high voltage DC due to arcing.

N channel MOSFETs are better than P channel due to the properties of the materials used in their construction. This makes them cheaper and more efficient.

They are generally easier to drive as the gate voltage is referenced to ground rather than the positive line.

I would use a low side N channel MOSFET to switch in the resistor.

Agree with the other answers here: the switch should be on the low side of the resistor.

If the resistor will be switched at a relatively low frequency, say below 5kHz, then very likely an IGBT will be a lower cost solution than a MOSFET, after taking all costs into account, namely: gate drivers, snubbers, and heatsink. Between 5kHz & about 10kHz both MOSFET & IGBT will be similar cost. Above 10kHz MOSFET becomes lower cost mainly due to the higher switching power loss in the IGBT requiring larger heatsinks.

You may need to consider an isolated gate driver to convert the signal from the MCU to something suitable to drive an IGBT or MOSFET. Switching frequency will have a significant impact on the selection of the most suitable solution for this role.