In the image provided, four different locations for Via that connect the power plan to the bypass capacitors are illustrated. My query pertains to determining the most effective model for delivering power from the power plane, along with the rationale behind this choice (A or B or C).

Additionally, sometime we have to choose D model for PCB layout. I seek clarification on whether the placement of capacitors depicted in the position of the D is appropriate. Ultimately, I aim to ascertain the most optimal method for placing both the via and the capacitor in this context.

Picture reference: The image was designed by myself in EdrawMax software.

enter image description here

This is the main circuit. I want to power the microcontroller from layer number three. Now, the question that arises for me is: where should I place the 3.3 V via for optimal performance?

My stack:

  • signal (I have the LCD in the top layer)
  • GND
  • power
  • signal

enter image description here

enter image description here

  • 2
    \$\begingroup\$ It's not clear what you're trying to express. Each VCC pin should have a capacitor to the nearest GND pin. If you truly mean that you want to connect two capacitors to one VCC/GND pair and leave the other un-bypassed -- both are wrong. If that's not what you're trying to express, then edit your question for clairity. \$\endgroup\$
    – TimWescott
    Mar 2 at 20:37
  • 1
    \$\begingroup\$ Are you sure this has not been asked before? Why are those 4 the only options, surely more exists. And the optimal position also depends what's under the chip. For example, if there is a ground plane right under the chip, the lowest inductance path could be none of the 4 options. \$\endgroup\$
    – Justme
    Mar 2 at 20:50
  • \$\begingroup\$ Hi @TimWescott I modified my question to make my point clearer, I hope it was useful \$\endgroup\$ Mar 3 at 17:33
  • \$\begingroup\$ Hi @Justme I put my layer assignment to be more clear for you \$\endgroup\$ Mar 3 at 17:35

1 Answer 1


This is two different questions. To get easiest access to the planes, you need via pairs close together and plane pairs close to the top layer. To get easy access to the cap, keep its trace pair tightly routed. You see it is always about the pairs, because you always try to minimize loop inductance.

Both, access to the plane and access to the cap make sure that the power supply impedance as seen from the IC is sufficiently small. In contrast, it is not typically a primary objective, to make the caps have easy access to the planes. That is why via patterns close to the IC are preferable, e.g. under the pins, ideally.

Good access between IC and cap can be provided through the planes, but doesn't have to. A cap can be directly wired to pins, if that forma a lower inductance connection.

If you use a standard stackup (with a large gap between L3 and L4), then your layer assignment is pretty terrible in terms of power distribution anyway, because the power plane and ground plane are not tightly coupled. As a result, wiring up the cap tightly to the pins is preferable, because going to/through the planes will be always bad.

  • \$\begingroup\$ I want to know which model Of via (A B Or C) is the optimum model for transferring power from the power plane (The third layer) to the bypass capacitor through Via. @tobalt \$\endgroup\$ Mar 3 at 8:28
  • \$\begingroup\$ @Alirezaagha30 transfer of power between the planes and caps is mostly irrelevant. I have updated the answer. \$\endgroup\$
    – tobalt
    Mar 3 at 8:30
  • \$\begingroup\$ I understand what you mean thanks. I was worried about high-frequency noise in the EMC test. I understand I should place via close the IC pin for minimum PDN impedance.@tobalt \$\endgroup\$ Mar 3 at 13:14

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