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I need to design an antenna trace (WiFi and Bluetooth) that connects an ESP32-S3 chip to an IPEX connector with an impedance matching circuit.

I have some constraints that I need to work around:

  • board space is very limited
  • minimum part size is 0603 as it should be hand solderable

I plan to have the boards manufactured by JLCPCB with 6 layers and 1mm PCB thickness. The stackup is (from top to bottom): SIG, GND, VDD, SIG, GND, SIG. Vias in pads are allowed in my design.

A 50 Ohm microstrip on the top layer with the second layer as reference has a width of 0.155mm according to the JLCPCB impedance calculator.

If I place the CLC matching circuit in the classic "pi" shape, I get this layout:

normal layout

As you can see, there's a lot of unused space, and the trace width varies widely, which will result in bad performance, I assume.

So I came up with this idea: Create a cutout on layers 2 and 3 (GND and VDD) and create a GND plane under layer 4 (SIG) under the antenna trace, which is connected to the main GND planes through the fencing vias. The 50 Ohm trace width for this layout would be 1.08mm, which is much more suitable for the pads of the parts of the CLC network. I also placed the parts closer together, so it looks like this: alternative layout

Would the second layout also work, or should I stick to the first layout?

Or should I ditch the matching network entirely? The ESP32-S3 design guidelines state:

For the antenna and the antenna matching circuit, to ensure radiation performance, the antenna’s characteristic impedance must be around 50 Ω. Adding a CLC matching circuit near the antenna is recommended to adjust the antenna. However, if the available space is limited and the antenna impedance point can be guaranteed to be 50 Ω by simulation, then there is no need to add a matching circuit near the antenna.

I do not have the means to measure and adjust the matching network anyways, so I would stick to the recommended values. Also, the choice of antenna that is connected to the IPEX connector is ultimately not in my hands. So should I just route a 50 Ohm trace from the antenna pin to the connector?

This is for an open source project, I do not intend to sell this design.

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  • \$\begingroup\$ hint: JLCPCB offers free assembly services. There's no need for you to hand-solder SMD passives in that case! \$\endgroup\$ Mar 4 at 17:58
  • \$\begingroup\$ That depends on your budget, if you're doing this for fun saving a few hundred bucks may be the preferred path, \$\endgroup\$ Mar 4 at 19:54
  • \$\begingroup\$ I like the second better, but perhaps you should simulate this in FEMM or build a sample and test with a VNA \$\endgroup\$ Mar 4 at 19:58

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The pi impedance matching circuit can only be populated if the antenna is known, as it's not, it can be left to be implemented on the antenna. Leaving the passives will get rid of the impedance discontinuity issue.

The impedance of the second design would probably need the surrounding ground plant to be furher away too, spending more area from the PCB.

By the way,

  1. I would stay away from placing vias on pads, unless absolutely necessary. Pin 14 it might introduce a problem with the solder flow. Others unnecessary thermal imbalance.

  2. I would "fan out" tracks from for example pins 2 and 3 of the IC, so that the pads stay the correct size. Otherwise solder mask will expose copper around the pad.

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