# Switching circuit with logic 3.3V control on p-channel JFET

The task is to derive sinewave (of higher frequency) chopped by step-function (also periodic but of lower frequency, i.e. several periods of sine wave are placed in that pulse). So I have a sinewave generator with frequencies up to 50 MHz, I have 3.2-3.3V logic levels from my STM32 with the desired duty cycle and I need to deliver 0.5 V amplitude sine wave with 1 V DC offset for my 50 Ohm load connected to the ground (i.e. cannot be placed above the drain). I hardly imagine how to deliver that sine pulse directly, so suppose we have a voltage buffer (with lil amplification) for the output. Also, it looks to me simpler to use JFET among other FETs because it's symmetric in drain and source. So far I only considered depletion mode P-channels, since it looked as winning solution having in general 0V Vgs as fully open and 3V Vgs as pinched-off. I've looked through a lot of models and analysis textbooks but yet cannot find the answer to the problem of having this 1 DC offset which appears on the drain as soon as the channel is fully open, i.e. can it burn the JFET and will it affect it's closing time and efficiency? If I added 1V DC bias to the gate terminal, would it be a solution or do I need some feedback from the drain? I don't see a case when it closes and opens completely. Please have a look at the figures below. I indicated Vgs of established ON and OFF states, however, I suppose transient process should be taken as well, especially time constants of formed RC-circuits, but I have no complete understanding of what MUST be calculated and what's the priority.

Currently, I can not manage even with this part, however, high-frequency effects should be included into the problem solution and if you have a piece of advice for that as well, you'd be helpful and I'd be enormously grateful.

• I strongly urge you to use a simulator to develop your circuit. Mar 12 at 12:55
• Thanks, perhaps for the sake of explanation I find it not more helpful, besides the question is about analysis by hand. I have simulations and they are not satisfying. Mar 12 at 13:01
• The golden rule with simulations is that if they say something won't work then, almost certainly, the real thing won't work. Your question doesn't mention analysis by hand. Mar 12 at 13:09
• JFETs are almost never the simplest option. There are rarely some uses for them, but enhancement-mode devices are usually easier to use, and no one makes enhancement-mode JFETs for obvious reasons. Mar 13 at 15:48

A simple circuit made with discretes isn't going to work well. In the past, I used to do things like this using a tranconductance->differential pair->transimpedance topology. Fortunately, it's a lot easier these days: there are excellent low voltage wide bandwidth analog switch ICs available. Have a look at the ADG701 to get started. Not a product recommendation: there are many similar parts available, and you'll have to choose the best for your purpose.

• Thank you for a simple solution, it worked out. Mar 29 at 5:57

I think you're going to have to go with a series/shunt switch configuration if you want much on/off ratio or at least reduce the 1M to more like 50Ω (more than 4 orders of magnitude!). Calculate how much the capacitive reactance is of your 'off' FET if you want to do hand calculations.

50MHz is a relatively high frequency. You might be able to get away with something like a DG419 SPST analog switch.

There are much higher performance (GHz) RF switch ICs available but they typically have issues with DC and are designed for lower voltage systems.

• DG419 is an old high voltage switch, but this is a low voltage problem. There are higher performance low voltage CMOS switches that work fine down to DC. Mar 12 at 14:23
• @JohnDoty I was referring to the newer GHz GaAs and Silicon-Germanium technology switches that are used in wireless kit. They usually require coupling capacitors. Eg. Skyworks. Mar 12 at 14:40
• Yes, I know. The are unsuitable here. But there are others that are suitable, with specs for switching 100's of MHz. Mar 12 at 17:11
• Thank you for the reply! If you're talking about 1MOhm at drain and approximate time constant formed with Cgd then I should mention this restriction is done to deliver the whole magnitude of the signal to the buffer. Having 50 Ohms there would result in at least 3 times less magnitude. Mar 13 at 5:37
• @Sombercy Yes, the problem is that it won't attenuate much when off. I imagine you are seeing that in simulation. Mar 13 at 5:39