I am testing a tool for verilog synthesis.I need to test that tool by using a library file or a directory but i am unable to get any example for the same.I am very new to verilog. Can any one suggest me any link for the same.

I had read on google that in any verilog file if we are using a library file, that means we had used the content of that library file.Its quite similar to using library file in C.

Also what does "decompile the original rtl in file" means.When i use synthesis tool , it always generate a intermidiate rtl output.I save that output in a file.Is that file is rtl file or there is some other rtl file which is to be decompiled to get some useful information.

  • \$\begingroup\$ As i read on wiki regarding rtl, it says A subset of statements in the Verilog language are synthesizable. Verilog modules that conform to a synthesizable coding style, known as RTL (register-transfer level), can be physically realized by synthesis software.SO what is actually orignal rtl file is?Decompiling orignal file means converting this level of verilog to the most simplest verilog level? \$\endgroup\$ – shailendra May 27 '13 at 9:19

I believe "decompile the original rtl in file" is the conversion of RTL coding to gate-level modeling. The RTL style has always blocks and assign statements, while gate-level modeling only contains calls to other modules and/or standard cells. Both are functional equivalent (when written correctly). Big difference is RTL is higher level of abstraction and therefore easier to code (especially complex designs), while gate-level modeling is closer to what the silicon design will actually be and can even simulate with annotated timing.

The library file contains the definitions of all the available standard cells for a particular technology and is used for RTL to gate level conversion. In other words it is the cells that the synthesizer is allowed to use for conversion. Typically it is hold definitions for nand, nor, xor, flop-flop, buffer, inverter, etc. and various flavors of each to support timing, load, size requirements. It usually provided by a vendor or foundry.

If you do not have Verilog library, but you do have a schematic. Then find out how to export the library as Verilog. Otherwise is it possible to make a fake library by hand (just realize you cannot use it with a real project). Example: fake_udp.v

module FAKELIB_NAND2(output OUT, input IN0,IN1 );
  assign OUT = ~(IN0 & IN1);
module FAKELIB_NAND4(output OUT, input IN0,IN1,IN2,IN3 );
  assign OUT = ~(IN0 & IN1 & IN2 & IN3);
module FAKELIB_NOR2(output OUT, input IN0,IN1 );
  assign OUT = ~(IN1 | IN0);
module FAKELIB_INV(output OUT, input IN );
  assign OUT = ~IN;
module FAKELIB_BUF(output OUT, input IN );
  assign OUT = IN;
module FAKELIB_BUF_BIGLOAD(output OUT, input IN );
  assign OUT = IN;
module FAKELIB_DFF(output reg Q, input CLK, RST_N, SET_N, D );
// ... more standard cells ...
primitive FAKELIB_DFF_PRIMITIVE(output reg Q, input CLK, RST_N, SET_N, D  );
   // CLK RST_N SET_N D : Q(state) : Q(next)
       ?    0     ?   ? : ? : 0;
       ?    1     0   ? : ? : 1;
       p    1     1   0 : ? : 0;
       p    1     1   1 : ? : 1;
      (?0)  1     1   ? : ? : -;
       ?    1     1   * : ? : -;
// ... more standard cells ...

Now Assume you have the following RTL:

module my_module(input clk, rst_n, input [2:0] in, output reg [2:0] out);
always @(posedge clk, negedge rst_n) begin
  if ( !rst_n ) begin
    out <= 3'b0;
  else begin
    out[0] <= ~(in[0] & in[2]);
    out[1] <= &in;
    out[2] <= in[1] | in[2];

Synthesizing with the fake_udp.v as your library will give something like this: (Note: Output depends on tool and options. Also this example was done by hand)

module my_module(input clk, rst_n, input [2:0] in, output [2:0] out);
supply0 SUPVSS;
supply1 SUPVDD;
wire syn_0, syn_1, syn_2, syn_3, syn_4;

FAKELIB_NAND2 U0 (.OUT(syn_0), .IN0(in[0]), .IN1(in[2]));
FAKELIB_NAND4 U1 (.OUT(syn_1), .IN0(in[0]), .IN1(in[1]), .IN2(in[2]), .IN3(SUPVDD));
FAKELIB_NOR2 U2 (.OUT(syn_2), .IN0(in[1]), .IN1(in[2]));
FAKELIB_INV U3 (.OUT(syn_3), .IN(syn_1));
FAKELIB_INV U4 (.OUT(syn_4), .IN(syn_2));
FAKELIB_DFF out_0__reg (.Q(out[0]), .CLK(clk), .RST_N(rst_n), .SET_N(SUPVDD), .D(syn_0));
FAKELIB_DFF out_1__reg (.Q(out[1]), .CLK(clk), .RST_N(rst_n), .SET_N(SUPVDD), .D(syn_3));
FAKELIB_DFF out_2__reg (.Q(out[2]), .CLK(clk), .RST_N(rst_n), .SET_N(SUPVDD), .D(syn_4));
  • \$\begingroup\$ i found some error which i am unable to debug in your verilog file.When i run your verilog file with the help of your library file ,it display some error PARSE_INFO 1]: Reading design file /home/shailendra/fake.v ..... [PARSE_INFO 2]: Analyzing module my_module ..... [STX_ERROR 50]: Line 1, syntax error. [PARSE_INFO 7]: Please correct above errors. \$\endgroup\$ – shailendra May 29 '13 at 13:47
  • \$\begingroup\$ Sorry about that. I fixed the typos, made sure it compiles and that the two versions of my_module are functionally equivalent. \$\endgroup\$ – Greg May 29 '13 at 16:02

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