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There is a question in my University exam requiring us to design a logic circuit for the following logic using the smallest number of transistors:

enter image description here

I was trying to optimise at the gate level by using NAND/NOR gates only as I know they are the gates that have reduction functions with the minimum number of transistors (four).

However, the answer of the question was wired to me where they have inputs at the MOSFET sources, as shown below.

enter image description here

I was wondering if such configurations are really allowed and used in practice in modern integrated circuits as I have never seen them anywhere before.

For modern IC design, do logic synthesisers optimise at the gate level (i.e. logic gates are the smallest units) or at the transistor level by realising arbitrary logic functions such as (ab + c) like shown below?

enter image description here

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  • \$\begingroup\$ Where is \$V_{DD}\$ in your first diagram? CG circuits at the input in CMOS ICs are, AFAIK, not used as their input impedance is quite low. Maybe after a buffer they can be used. \$\endgroup\$
    – HarryH
    Commented Mar 19 at 3:44
  • \$\begingroup\$ @HarryH There seems to be no $V_DD$; this was the exact answer given. Also what does CG stand for? Thanks. \$\endgroup\$
    – ZHZ
    Commented Mar 19 at 11:35
  • \$\begingroup\$ Ok. 'CG' stands for 'common gate'. Here the source terminal is the input and the gate is then connected to ground. Here the gate is also an input, but the source terminal doesn't know that and just sees a rather low impedance. \$\endgroup\$
    – HarryH
    Commented Mar 21 at 20:52

2 Answers 2

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It was very common in TTL era. However, the input impedance is usually lower compared to gate controlling.

enter image description here

Source: https://commons.m.wikimedia.org/wiki/File:TTL_NAND_003.svg

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It's unconventional and you'll probably have issues with the logical threshold and current bias for the family you are targeting. However if it works reliably go for it.

As for manufacturing: design is done using macro cell defined by you silicon process (usually). So you generally work at the gate or pseudo-gate level. You have a NAND block, a transmission gate block and so on, the synthesis tool uses them.

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