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I have a question about operating point of cascaded NFETs that I carry with me quite some time. I hope someone is able to give me some hints or insights here.

It boils down to this:

When you have a cascode of N-channel MOSFETS with controlled or fixed gate voltages as shown in the following circuit, what voltage levels do the drain-source voltages of M1, M2 and M3 take?

Cascaded MOSFETs circuit

What makes this circuit complicated is that the MOSFETs M2 and M3 have a fixed gate voltage and the gate-source and drain-source voltages are the "variables". U2,M1 and R4 form a current source with 9.39mA, so the voltage on drain3 is fixed.

What I don't understand is that there is a lot of ambiguity between the drain-source voltages of M1,M2 and M3. If M1 has slightly lower drain-source voltage, then M2 or M3 might get higher drain-source voltages to compensate.

From simulating all MOSFETs with 3 different threshold voltages (1.6V, 1.8V and 2.0V) I see that V(drain2,drain1), the drains-source voltage of M2 does not change. What is the reason for this? Is there a way you can you calculate the operating points of drain1 and drain2 given the MOSFETs specifications?

Drain source voltages of cascaded N-MOSFETs

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    \$\begingroup\$ The MOSFETs are connected in cascode not cascade. Trivial maybe but, if it helps in googling maybe not. Is V(drain2,drain2) a typo? \$\endgroup\$
    – Andy aka
    Mar 19 at 12:01
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    \$\begingroup\$ Cascode has a property of 'shielding' - that is Vd1 is kept almost constant when Vd2 changes (of course the assumption is that all transistors are in the saturation region). So my guess is that Vd2's value is not that important as long as M2 and M3 are saturated. I don't know why is this, so I'd love to know the answer to that as well. \$\endgroup\$
    – Jack Black
    Mar 19 at 12:18

1 Answer 1

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When the source is permitted to rise above ground in potential, by placing something with impedance between source and ground, you have a source-follower. this is the case for every single MOSFET in your schematic. Each transistor might be viewed like this:

schematic

simulate this circuit – Schematic created using CircuitLab

\$R_D\$ and \$R_S\$ represent arbitrary impedances, their values won't be important in the following arguments.

If any current \$I_D\$ is flowing, then the transistor must have a \$V_{GS}\$ close to or above the transistor's \$V_{GS(TH)}\$, since that's the only condition that would permit \$I_D>0\$. Extending this argument to all the transistors in the chain, if any current is flowing through their channels, then they all must have \$V_{GS} >= V_{GS(TH)}\$.

Consequently, source potential \$V_S\$ of any MOSFET here cannot rise above \$V_G - V_{GS(TH)}\$, since if it did, the transistor would be off, and would not be able to raise \$V_S\$ any further. By this argument, if any current is flowing, and all the gates are held at potentials close to 3V or so, all the sources will be in the vicinity of \$+3V - V_{GS(TH)}\$.

These arguments apply to all the MOSFETs here, but if we focus for a moment on the top one, M3, it's clear that M3's source cannot rise far above zero, since its gate is held at \$V_{G3} = V_{CASC2} = +3.3V\$. Consequently, M2's drain is also constrained, and will always be within a volt or so of zero, as long as some drain current is flowing.

Now looking at the lowest transistor, M1, you are biasing the gate in a closed loop, the intention being to have drain current \$I_D = \frac{V_{REF}}{R_4}=9.39mA\$. If that current is actually permitted to flow, then source potential will be exactly \$V_{S1}=V_{REF}=0.833V\$, and importantly, M1's drain (which is M2's source) cannot be lower than that.

All things considered, then, the drain of M2 is constrained:

$$ V_{D2} < V_{CASC2} - V_{GS(TH)} $$

The source of M2 is also constrained:

$$ V_{S2} > V_{REF} $$

That's why you don't see much variation in \$V_{DS}\$ for M2.

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    \$\begingroup\$ Really great insight, exactly what I was looking for. Thanks a lot, Simon! \$\endgroup\$ Mar 19 at 13:43

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