I´m using the LSM6DSR accelerometer/gyroscope from ST on a project. Looking into the application hints, it suggests using a 10k resistor as pullup for SDA AND SCL:

LSM6DSR I2C pullup sugestions

Since I´m using another slave (PCF8563TS) on the I2C bus, I tried calculating the resistor needed for the application. My result was Rp(min): 775 Ω and Rp(max): 885.16 Ω

The microcontroller uses 3.3V, the maximum capacitive load for each bus line on both I2C devices is 400pF, the maximum rise time of both SDA and SCL signals is 300 ns, maximum output voltage low is 0.2V and maximum sink current is 3mA.

Why does the value in the datasheet differ so much from my calculations? Would it still work if I used a 10k resistor?

  • 5
    \$\begingroup\$ No one can guess why it differs when you don't show your calculations. \$\endgroup\$
    – pipe
    Commented Mar 19 at 14:43

2 Answers 2


Very good question, and the explanation can get lengthy.

For starters, you have used 300ns rise time and 400pF for calculations to end up with 885 ohms. That is correctly calculated, but actually it makes no sense for many reasons.

The first thing to notice is that the 300ns requirement is for Fast Mode up to 400 kHz.

And the second thing is, you can't achieve 400 kHz with 400pF, unless your chips can achieve 6mA output sink current at 0.6V output voltage. Or at least, you can't achieve it with just simple resistors as pull-ups, but can use a current source.

So in real life, to achieve 400 kHz, capacitance must be much less than 400pF to allow for rated bus current, or if you have 400pF, you can't communicate at 400 kHz, and you must even go outside of the required 300ns rise time (which technically is allowed under the specs, in the chapter that describes how to work beyond allowable bus capacitance).

And if you allow for only Standard Mode speed up to 100 kHz, you are allowed to have 1000ns rise time at 400pF.

So, there are the specs that define things, and under certain scenarios, with chips rated for stronger IOs and suitable voltage thresholds, you only need to be within limits of the chips you have.

But frankly, having a 400 kHz bus at 400pF is not achievable. In practice, your bus has less capacitance, unless you have I2C going over long cables. If your data rate allows, maybe stay within 100 kHz bus speed.

10k pull-ups will work, but requires the bus capacitance to be low.

If you simply rate the pull-up around 3mA, you get minimum of 1100 ohms (no margin). 4k7 pull-ups will allow up to 70pF of capacitance and 300ns rise time is possible which allows up to 400 kHz.

The 10k examples allow for 30pF and up to 400 kHz, or 100pF up to 100 kHz, but does not really allow going past 400 kHz to Fast Mode Plus requirement of 120ns rise time.


As long as the bus is no longer than a few centimeters, I can't imagine the capacitance of the bus exceeding 100pF or so, even with several devices attached.

The 300ns rise and fall time requirement is tight, but achievable with a reasonable pull-up resistance. For 100pF bus capacitance, \$R_P\$ is:

$$ R_P < \frac{300ns}{100pF} = 3k\Omega $$

2.2kΩ would place you well within the required rise and fall times, and require the transmitter to sink:

$$ I = \frac{+3.3V}{2.2k\Omega} = 1.5mA $$

That's also reasonable. The PCF8563 datasheet is a little ambiguous regarding what 3mA means, but I believe that it means any load up to 3mA will be fine. I couldn't find any sink current specs for the LSM6DSR, but I would be confident that any modern I2C output can sink 1.5mA.

I would not recommend using 10kΩ, unless the bus is extremely short, and you have very few (<4) devices attached.


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