I am a student and this is my first time doing a PCB. I am wondering if it's more optimal to designate both ground planes with the same net, or have them as DGND, AGND, and use a net tie.

I have a space constraint where the board needs to be 30x30mm. I chose a 4 layer sig, gnd, gnd, sig stackup. I have my digital signals on top, and analog signals on bottom. My power is routed on the signal layers. One sensitive component I have is the AD7124, which is on the bottom of my board. I guess my biggest fear is overcomplicating things and inadvertently introducing more noise.

The articles I read always mention splitting a SINGLE ground plane in the XY direction, but I need to know if it's appropriate to have different nets for the two internal ground planes.

  • \$\begingroup\$ You've told us there's a possible noise-sensitive component, but have not mentioned what is the potential source of noise that you fear may inavertently introduce more noise ? Are you talking very fast digital circuitry, or some CMOS gates etc ... just to understand better. \$\endgroup\$
    – citizen
    Commented Mar 20 at 9:26
  • 3
    \$\begingroup\$ Check out a video of Rick Hartley by Altium, titled 'How to achieve proper grounding', two hours of valuable lesson, which will answer this and future questions. \$\endgroup\$
    – smajli
    Commented Mar 20 at 10:19
  • \$\begingroup\$ If you're concerned about digital noise, keep the ground planes separate and join them at only one point, possibly through a ferrite bead. \$\endgroup\$
    – DELTA12
    Commented Mar 20 at 16:55

2 Answers 2


You need to engineer it such that the return paths for the digital signals and other noise inducing nets like switch mode supplies don't cross the analog signals that feed your AD chip.

Just splitting the two with a net tie won't by itself help nor necessarily will it hurt.

Imagine you have engineered it perfectly so that all the 'noisy' return currents are away from the sensitive stuff. Now it doesn't matter that the two GND planes are one net because the currents don't interfere with one another.

Imagine you haven't engineered it that way. The return currents will follow the path of least impedance, but will now cross over one another. The more stitching GND vias there are, the shorter that return path will be, minimising the impact of the noise. Now if you delete the stitching vias and you introduce the net tie at a single point in the PCB instead, all those poorly engineered return currents are going to have to flow through AGND to the net tie back to DGND and then find their way back to where they are actually trying to go. AGND will see noise at the net tie for sure. In my mind using a ferrite bead as a net tie in this same situation could actually make it worse.

30x30 isn't much space to keep noisy digital stuff from sensitive analog stuff, especially if the analog stuff is in the audio frequencies or lower. You might find some filtering can help.

And finally if you really have got all digital on top and all analog on the bottom that's a great start. You now just have to think very carefully about the place where the two meet, like at an ADC with SPI on one side and analog on the other. Make sure the digital Comms and control signals have stitching GND vias really close to where the signals cross from L4 to L1. These will keep the return currents away from the analog power pins and signals.

  • \$\begingroup\$ This answer makes perfect sense to me. I will use a single GND net for both internal layers and introduce the stitching vias. Thank you for your help. \$\endgroup\$
    – amill
    Commented Mar 21 at 10:06

If - as you are implying - the offenders are routed on top and the victims are routed on bottom, most likely, splitting your GND in any way won't have any advantages, because their respective fields shouldn't share much space.

Generally speaking, having separate AGND and DGND on PCB level or splitting GND is a bad idea in 90 % of cases anyhow.

The reason why many ADCs have separate AGND and DGND pins is that return currents from switching events in the digital section of the ADC don't share the in-package-return-path with the analog section: Some parts of the in-package-return-path are relatively high inductance (typically package pins and bonding wires) so switching events in the digital section (high di/dt) cause voltage drops on those high inductance parts. This could cause interference with the analog section by lifting the analog section's ground above PCB ground (also known as "ground bounce"), if analog and digital section share the same return path.

But solid GND planes offer a low enough inductance so there is usually no point in having separate AGND and DGND on PCB level. Avoiding shared return paths with careful part placement and signal routing (as you probably did already) should be sufficient in most cases.


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