I'm looking at different FPGAs for my dissertation project and I keep seeing that the multiplier blocks are 18x18 bit, why is this? Why are they not 16-bit?


Why not? Really, it's completely arbitrary. The cost in terms of chip area for 18×18 bits vs. 16×16 bits is negligible when compared to the area used for all the other resources (especially routing) on an FPGA. If you don't need the extra bits, just ignore them.

However, I think the common practice of making multiplier blocks 18×18 bits has its basis in the fact that the on-chip memories of many FPGAs are mutliples of 9 bits wide.

Why are memories 9 bits wide? Well, 9 bits allows you to store 8 bits plus parity, or 64 bits plus 8 bits of ECC (72 bits total). Applications that care about data integrity can make good use of such memories.

However, there are lots of applications that don't need the 9th bit for protection and would prefer to use it for extra precision in the data. It just wouldn't make sense to design a chip that can store data in 18-bit chunks, but can only process 16-bit chunks.

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    \$\begingroup\$ +1 for the "Why not?" :-) \$\endgroup\$ – Anindo Ghosh May 27 '13 at 16:00

I think it stems from the memories.

They were 18-bits already (to allow a parity bit per byte) and had been for a generation (of FPGAs, not engineers!) or so before multipliers came into the picture. And given one of the big uses was for FIR filters, then for applications where parity was not needed, having 18-bit coefficients is better than only having 16-bit coefficients, as the silicon area increase is very small.


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