# How do I decide the bandwidth of a driver through 'input transition rise and fall rate'?

I am carrying out a design with a driver:74LVC1G125 datasheet of 74LVC1G125. Signal that will go through this driver is about 600khz so I have to know the bandwaidth of 74LVC1G125. I have read the datasheet and I can not find anything about bandwidth but an unknown parameter:input transition rise and fall rate.

I think it must has something to do with the bandwidth of 74LVC1G125 and I find a description about itinput transition rise and fall rate.Unluckily, it makes me more confused that this parameter is about the amount of ground current. So can anyone give suggestions about bandwidth of this driver?

• i know a relationship i.e Bandwidth=0.35/rise time.i don't know whether you can apply here or not, wait for others answer. May 27, 2013 at 15:17

Bandwidth isn't the term your looking for, you want to know what the maximum operating frequency or switching rate is. Look to table 11 snipped here.

I'd use max numbers, so at 5.0 V and room temp you can run that at 4.0 ns + 4.0 ns = 8.0 ns which is 125 MHz. The IC will run that fast but it may not be useful for you unless you can make sure that you can handle the variable delay in subsequent circuits.

• I have another question. I know that Tpd=max(Thl,Tlh). so why does pulsing two Tpd equal to the period of the fasted signal that goes through this driver? May 28, 2013 at 1:02
• You have to make sure that the applied signal stays on the output long enough for the signal to propagate through. So you need the Tpd on the rising edge and the Tpd on the falling edge. May 28, 2013 at 1:07
• I must make some mistaskes. A period of signal does not only inculde Ton and Toff but also the time that signal stays high and low. so what are parameters of high or low period? May 29, 2013 at 1:05
• Those numbers are for the determination of the maximum (and probably not very useful) clock rate, as mentioned above. As long as you are running slower than that number the Ton and Toff will be determined by other factors. May 29, 2013 at 1:22

Notice that the input transition rise and fall times are maximums, not minimums. These indicate the slowest rise and fall times you should provide at the inputs. Slower edges might cause the output to chatter as the input voltage passes between the valid input high and low levels.

To find the maximum data rate the device can handle, you need to look at the propagation delay specs:

Even taking the worst case scenario, a 1.65 V Vcc at 125 C, the propogation delay is 10.5 ns. For a full cycle of a periodic signal you'd need 21 ns, meaning this chip can handle signals into the 10's of MHz.

At 600 kHz you'll have no problem at all.

Firstly, your table is telling you that the recommended rise/fall rates for inputs to the device are 10ns/Volt - it is saying to you, that for a 5V supply, do not feed inputs to the device that are slower than 50ns. OK slower inputs won't damage the chip but the recommended condtions are what they are - it's a manufacturer's get-out clause in a way.

You need to be looking at table 11 - dynamic characteristics/propagation delay

This tells you that on a 5V supply an input change will take typically 1.7ns to get to the output. Figure 8 shows a picture and note that on this device Tpd = Tphl = Tplh so it is symettrical.

I guess this just about means you could get a 250MHz clock through it - it won't be pretty but it'll get through. Designing with typical values is a risky business and better to use maximum values.

EDIT - your 2nd link is also telling you about the input rise/fall rates - too slow a rise or fall on the input will cause larger-than-normal earth currents that can cause a glitch in the output and this can ultimately cause multiple glitches. Ensure your 600kHz signal has rise/fall rates below this value to prevent unpredictable results.