# Why do we add the positive clock skew to the minimum clock period?

Given the following circuit:

I was told that the minimum clock period would be the sum of the setup time plus the propagation delay plus the clock skew for a positive clock skew. I was wondering as to why we add the clock skew to the time period when it is positive because a positive clock skew would only decrease the time the value of QA can be held. Don't we just have to check if the propagation delay is greater than the hold time plus the time skew? How does adding the clock skew solve any issues?

• I guess it comes down to what you mean by positive clock skew. In your picture is it Tcb-Tca, or Tca-Tcb? That is, one of your two clocks (or a 3rd?) has to be you reference from which the skew to the other is measured. Commented Mar 23 at 0:41
• And what do you mean by propagation delay? Is it just the prop time of QA along the trace? Or does that include the clk->Q delay of the first flip flop? Commented Mar 23 at 2:29
• By positive clock skew, I mean positive when Tcb-Tca is positive. By propagation delay, I mean both the combined delays of the prop time of QA along the trace and the clk->Q delay of the first flip flop. Commented Mar 23 at 4:04

The cycle defining reliably getting data from Qa to Db will have three basic components:

• Clock-to-Q (Tcq) of Qa (not sure why they didn't mention this)
• Prop delay (Tpd, time-of-flight) from Qa to Db
• Db setup time (Tsu)

This assumes CA and CB have no skew.

Let’s define Tskew as T(CA) - T(CB). We then have a cycle time of:

• Tcyc = Tcq + Tpd + Tsu + Tskew

What does this mean? A positive value for Tskew slows down your cycle, while a negative one speeds it up.

If CB is later than CA, you can deduct this inserted delay from the achievable cycle time. That is, Tskew = T(CA) - T(CB) is a negative value. This is sometimes called helpful skew (but mind the hold time).

Think of it this way: by moving the receiving flop’s clock later, you’re also moving its sample window later. This gives more setup time. You get this when Tskew is negative.

In the other hand, if CB is earlier than CA, then you add this delay to the achievable cycle time (but it helps hold time). That is, Tskew is positive.

Let's work some examples. Say you have these parameters for your flops:

• Tcq = 3ns
• Tpd = 1ns
• Tsu = 2ns

Without considering clock skew, adding them together we get a best-case cycle time of 6ns.

Now, let's add 1ns delay to CB relative to CA:

• Tskew = T(CA) - T(CB) = (0ns) - (1ns) = -1ns
• Tcyc = (Tcq + Tpd + Tsu) + Tskew = (3+1+2) + (-1) = 4ns.

Delaying the receiving flop achieves a shorter cycle time. Again, this is helpful skew.

However, if we instead delay CA with respect to CB, Tskew is a positive value:

• Tskew = T(CA) - T(CB) = (+1ns) - (0ns) = +1ns
• Tcyc = (Tcq + Tpd + Tsu) + Tskew = (3+1+2) + 1 = 7ns.

This is unhelpful skew as far as cycle time, but it improves hold time.

Many board-level systems with ICs sharing a clock are made this way: they will feed the clock to the receiver first, then the transmitter, in order to ensure hold time. It's a compromise to ensure system reliability without having to think too hard.

More advanced designs (boards and chips) will seek to minimize clock skew by using clock trees that seek to balance the clock distribution delay between flip-flops, ensuring best possible cycle time without compromising hold time.

In the bigger picture, when designing a clocked system you need to consider variations in all the paths to establish reliable timing, both setup and hold. Clock skew uncertainty will influence both.

• I'm confused because my class said we should add the skew to the time period when CB is later than CA, but they didn't explain why. Commented Apr 2 at 2:36
• You always add the skew. It’s a question of the right skew equation. It’s transmit flop clock (CA) - receive flop clock (CB). Then the sign comes out correctly. Commented Apr 2 at 2:57