# Stability of a constant current sink( opamp+nmos)

I am using opamp and a mosfet as constant current source. My current is from 0mA to 25mA.

Opamp-TLV9002 (GBW-1Mhz at 5v , phase margin - 78deg at 5.5v and gain as 1 )

Mosfet- nmos- Bss123lt1g ( input capacitance -20pf , Rdson - 6 ohms )

The opamp is unity gain stable. So do I have to use R63,R64,C4. I've read it helps to reduce oscillation. Stability of Constant Current circuit

Q1. I want to understand the limitations of my circuit. If it does start oscillating then why it is. Does the resistance of the mosfet(rdson) also matter? What calculation should I do to know before hand whether or not it will oscillate. I have to find the alternatives for the mosfet and opamp, so would like to understand which parameters I should be looking for. The other mosfet that I have has Rdson of only 48 milliohms.(cdm3400). If it oscillates then how to choose the R63,R64,C4 values.

Q2. Lets say all of the bottom mosfet(NMOS19,20,21,22,23,24) are open and I am giving a signal of 5v on IN2+ pin, will it still be reflected at IN2- pin? If it does then won't that voltage travel from the body diode of NMOS25 to the drain of that mosfet and if D2 is not present then I can have 5v at OP2-GRD? OP2-GRD is an ground for the system and should not have any voltage present on its terminal.

If someone wants to understand the circuit, have given general description below the image.

The user will provide 24v to the OP2-GRD(top of the circuit). The OP signal on U4 is provided by DAC(0-3.3v). There are 2 constant current source. 1 circuit will provide a constant current of 2mA or 4mA as a offset and the second circuit the actual signal.(eg-Output is 4-20mA and 8mA has to flow then 4mA offset is given by 1 circuit and other circuit gives the 4mA signal). Such an architecture is chosen because the system architecture demanded so. The n-mosfets at the bottom are to be selected based on the output signal user needs. If user needs a signal from 0-20mA then NMOS23,NMOS24 will remain open thus giving no offset.NMOS21,22 will also remain open. NMOS19,20 will be turned on thus giving an effective resistance of 150 ohms. If DAC gives 3v at OP I will get 20mA flowing. Question is can this be implemented(mostly yes, will have to test it)

You are asking about circuit conditions caused by specific component values, but the values are not given. Thus, speculation.

R63 and R71 can be eliminated. They usually are in a gate circuit of a switching power supply, motor driver, etc., to prevent ringing caused by very fast gate drive edges, gate capacitance, and lead inductance. These conditions do not apply to a small-signal FET operating in an analog mode.

IN2+ is connected to the opamp's positive rail. Pretty sure this means that the right side current source circuit will not work.

This looks like school work. The reasoning behind C3 and C4 given in the thread you linked is pretty clear. Please explain your understanding of the reason for C3 and C4 in the circuit.

• why won't the right side circuit work? I am giving 5v and nmos23 is conducting, I will have 5v/2500ohms = 2mA flowing right? Commented Mar 24 at 17:07
• For the feedback loop to close, IN2- must equal IN2+. It cannot, because the output cannot exactly equal the chip's own V+ at IN2+. Plus, there is the voltage drop from the chip's output (the FET gate) to the feedback point (the FET's source). Commented Mar 24 at 19:13
• The opamp gives rail-rail to output so it will give 5v as output. Commented Mar 25 at 9:00
• Not physically possible. The datasheet says 20 mV less than the positive rail, which is greater than the input offset voltage. And again, what about Vgs? Commented Mar 25 at 12:48
• input offset voltage is 2mv max. ok I will get 4.980 v ,then why wont the mosfet turn on? Instead of saying won't work can you say what is the problem so even ill understand your point. Commented Mar 25 at 16:37