I would like to use the MIC5014 to drive an N-channel MOSFET as a high-side switch. My supply voltage in this system is 24 V. I understand that the MIC5014/MIC5015 uses an internal charge-pump to bring the gate of the power FET above the supply voltage, and that it uses a Zener diode to prevent the charge pump from going more than 15 V over the supply voltage. So ultimately the gate voltage would reach 39 V, but this would not be a concern since voltage relative to the source (Vgs) would only be 15 V.

What I am concerned about is negative Vgs when turning off the MOSFET. If gate of the power FET was pulled down to its source, there would be no concern as Vgs would be zero. But my amateur reading of the MIC5014 block diagram leads me to believe that the power FET gate is pulled all the way down to through a diode. Wouldn't that cause a Vgs of -24 V, exceeding the -20 V minimum Vgs of almost all FETs? If so, what should I do instead?

The block diagram from the datasheet is as follows:

MIC5014/MIC5015 block diagram


2 Answers 2


FYI, this style of high-side driver is a bit peculiar, and, I think, makes a number of special-case assumptions. In short, you are right to be concerned; whether that concern manifests in any given example, depends.

The typical use-case, as a high-side load switch, has the load either pulling down to ground immediately at turn-off, or the load is absent and gate current pulls down the output directly (source may end up somewhat negative as Ciss dominates over Coss). Typical loads would be resistive or inductive, such as lamps or solenoids -- applications in automotive and industrial automation, for example. A capacitive load, which does not self-discharge as fast as the gate drive does, would be the most prominent risk scenario.

Also, you can always put a source-gate diode (or zener, if you want additional Vgs(on) clamping) in the circuit to prevent excessive reversal, so it's not exactly a big deal. But it is kind of weird to need that in the first place, when a source connection is already available, and it's not like you're going to use it with anything but an N-channel enhancement mode MOSFET so they could've just put it in there to begin with, or wired it differently. I'm not sure offhand what other applications or arrangements they might've designed for (but, there are the application examples to look at).

There are several other discrepancies with the specifications of these parts, and I would discourage their use in new design. I would at least want to see a more detailed internal diagram, or reverse-engineered die photo; what the charge pump is, what the PMOS is doing (my guess is on discharging the internal charge capacitor into the output, but if it's the kind without an external capacitor pin, that won't amount to a whole lot: even 10pF is "big" for a capacitor onboard an IC), what happens at extremes of pin voltages or currents, etc. But for all that effort, I'd just as well spring for a better-behaved part.

Alternatives, then.

The more common/traditional gate drivers use a source-referenced driver circuit, usually in a HVIC process where the high side is practically a separate die, yet in fact is integrated on the same chip through special processing to give the high voltage withstand. These are normally combined with more-or-less identical logic on the low side, plus level-shifting circuitry that spans the high-voltage boundary, to make a dual (half-bridge) driver.

The trouble is getting power to the high side.

Usually, power is delivered by bootstrap, which means high side 'on' duration is limited by bootstrap capacitance, and the switch node must always be brought down to GND (or a little below) to recharge it inbetween.

This can be substituted with an external charge pump, at least for application up to a modest voltage. The catch is, when switching regularly, the switch node's change (delta V and dV/dt) pumps the charge pump by itself, overloading the high side; a zener/TVS is required to dump excess charge the driver isn't using. Above 100V supply or so, it gets dubious to use a large enough coupling capacitor, even at high frequency, to supply enough current through the charge pump in steady-state (these typically draw ~0.3mA quiescent current), while also respecting peak current ratings of the components used to build the charge pump (usually another gate driver channel, plus rectifier diodes).

The most general alternative is a DC-DC converter, with true isolated output, which is usable up to whatever voltage rating the isolator and driver are rated for.

You can further use a low-side driver, with a digital isolator to couple the signal, and make a fully isolated driver; this is most attractive for industrial applications, where switching currents and/or voltages are high enough that common mode / between-grounds voltage limits (of the bootstrap HVIC type) cannot be respected, or when for other reasons the control must be isolated. Fully isolated ICs are available, DC-DC converter included; they are relatively expensive chips, but the component count reduction is substantial, and such applications typically have the budget to accommodate these parts.

  • \$\begingroup\$ It's very helpful to know this is a "wierd" part. I will use a DC-DC converter with a gate driver and optocoupler next time. I did end up building a circuit with this part, and while it did switch the load there was a huge oscillation (12Vpp) that would occur when switching on. It was almost like the gate voltage was varying a lot in the linear region while the charge pump was getting up to the full voltage. Also... I observed other components burning out, as if 24V was somehow getting onto the 3.3V rail. \$\endgroup\$
    – BonsaiOak
    Commented Apr 21 at 6:23

It is a concern. The MOSFET datasheet always lists Vgs as a +/- number after all. High-side drivers should be taking this into account, and I think this one does.

Notice where the control input runs. It runs to four places:

  1. The charge pump
  2. The PMOS.
  3. Pulldown NMOS to ground through a diode
  4. NMOS to short gate and source

(1) is responsible for turning the MOSFET on.

(2) The PMOS is a bit strange here. The IC advertises load dump protection which seems to be why the PMOS is there. However, as shown, that simple PMOS circuit will not protect against a load dump. Additional circuitry is required at the gate to do this and I suspect there's actually quite a bit circuitry more at that PMOS gate than is shown.

(4) is what is responsible for turning a high-side NMOS off. (3) is responsible for turning a low-side NMOS off. It looks to me like the diode is there to provide a fixed voltage drop that allows (3) to override (2). But how it does so is a bit unclear. I am pretty sure what is shown is not exactly what is in the IC.

  • \$\begingroup\$ "I am pretty sure what is shown is not exactly what is in the IC." I got the same impression. DS claimed some things which didn't seem possible given the diagram. I appreciate the feedback that this is real and not just me being unfamiliar with the technique. \$\endgroup\$
    – BonsaiOak
    Commented Apr 21 at 6:16

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.