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I have a chip with 14-bit LVDS input data lines (DATA0P/N to DATA13P/N) on the chip DAC3174. I don't have enough space left to route all these data lines, so I chose to set the two least-significant bits (LSBs) to permanently HIGH or LOW. I know that LVDS has common-mode voltage of 1.2V, V_OL of 1V and V_OH of 1.4V (so a peak-to-peak differential voltage of 400mV) just as it's shown here:

enter image description here

I thought about this resistor network:

enter image description here

On the left side the voltage is 1.26V at the input of the chip, so the pin would see a permenant HIGH. On the left side the the P/N are reversed, while the voltage stays the same, P is at VSS and N is at VCC, so the pin would see a permenant LOW.

Here's also the table of the DAC3174 chip about the DATA lines: enter image description here

Will this work as intended? I will eventually use zero ohm resistors to switch between both cases. Please suggest a better solution, if this network isn't optimal for this purpose.

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    \$\begingroup\$ @Aaron The differential input has internal 100 ohm termination. \$\endgroup\$
    – Justme
    Commented Mar 27 at 17:41
  • \$\begingroup\$ @Justme what do you mean? Yes! Internally the data lines are terminated with 100 Ohm resistors, but this shouldn't change the network function correct? \$\endgroup\$ Commented Mar 29 at 13:31

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Yes, this should work fine.

As noted in the comments, the input has a built in 100R termination. It is in fact this termination that makes the circuit work. This has a range of 85R to 135R, which may have some impact on the common mode and differential voltage range, but should still be in spec at both extremes.

With the 100R in series with the other two resistors, you get a voltage of 300mV from P to N, with a common mode voltage of approximately 1.2V. Both are well within the specifications for an LVDS input, and will provide a suitably strong 1 or 0 (depending on which resistor you connect to the pullup).

Circuit simulation showing resistors and internal termination

With the voltages in spec, there is no danger of damaging the inputs to the chip - it's no different from feeding the receiver with a continuous stream of zero bits from a normal LVDS transmitter.

Note that each input bias network will sink about 3mA of current, but that is no different from what you would get with a normal driver, and can't be improved on because the internal termination prevents using higher value resistors to provide the bias.

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