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I have almost finished my first 4-layer PCB design using Signal(Top)-Ground-Power-Signal(Bottom) stack-up and have some questions before sending it to production. Due to the very tight space on the top and bottom planes, I had to pass RGB LED PWM signal traces on the top signal layer through the power plane to the bottom layer across the 5V power supply ground rail, where the filtering with decoupling capacitors is made. These three orange colored traces can be seen in Figure 1, where they switch to blue colored bottom layer through vias. In Figure 1 only bottom and power layers as well as top and bottom component margins are visible. Since these traces split the part of the power plane, which is a reference for the bottom 5V DC supply ground rail, does this cause EMI issues in my board? How should I mitigate the effects of it? Should I use jumpers and 0 Ohm resistors?

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My second question is about UART and I2C signal trace clearances. I have used 0.25 mm wide traces for UART signals. Is it safe to keep a clearance of 0.25 mm between each trace in order to avoid signal coupling and integrity issues?

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Thank you...

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Your issues with the LED lines bring up two issues. One is the interruption of the return path for any signals crossing the gap. The return currents have to find their way around the gap, creating a loop antenna where you wanted a transmission line.

The second has to do with the current flow in your ground plane. Gaps in the ground plane can act as slot antennas.

If it's absolutely impossible to implement these on the top/bottom, another approach would be to run them around the edge of the board instead of through the middle.

Both of these concerns are also present for the slots you've created with lines of vias spaced so closely that there is no ground plane connection. If it's possible to stagger those so the pad clearance areas don't overlap, you're better off. Another approach is to reduce the pad size to zero on the planes they're not connecting to, which makes the pad clearances smaller.

As far as the RS232 and I2C lines, 0.25mm spacing has always worked for me. These signals are slow enough that they don't need much in the way of precise tuning; you primarily need to ensure the edges are monotonic. Most signal integrity issues I've seen on I2C are due to improper selection of pullup resistors.

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  • \$\begingroup\$ Thank you Cristobol, although it have been a little cumbersome, I have revised the PCB to have a single monolithic power plane. \$\endgroup\$
    – Semih
    Commented Apr 1 at 9:03

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